Wisetphanichkij, Sompong

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Wisetphanichkij, Sompong
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sompong.wi@kmitl.ac.th

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    Item type:Publication,
    The combinational and sequential adiabatic circuit design and its applications
    (2009-04-08)
    Wisetphanichkij, Sompong
    ;
    Dejhan, Kobchai
    In this paper, a new design of adiabatic circuit, called the quasi-static efficient charge recovery logic (QSECRL) is proposed. To achieve minimum energy consumption, this paper proposes a technique to reduce channel resistance and remove diodes from the signal path. This design method can be implemented in both combination logic and sequential logic. The counter circuit and the 8-bit carry look-ahead (CLA) circuit, a more complex circuit, are selected to evaluate this proposed design. All simulations in this paper have been implemented by SPICE with the 0.8 μm MOSIS technology MOS transistor model under 2-volt (peak-peak) sinusoidal power-clock supply. The results show significantly improved performance of the 8-bit CLA circuit with 20-30 fJ and 70 fJ energy consumption at 10-100 MHz and 500 MHz operating frequency, respectively. © Birkhäuser Boston 2009.