Chivapreecha, Sorawat
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Preferred name
Chivapreecha, Sorawat
Alternative Name
Chivapreecha, S.
Chivapreecha, Sorwat
Main Affiliation
Email
sorawat.ch@kmitl.ac.th
5 results
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Item type:Publication, Continuously Tunable Frequency and Phase Biquad Oscillator(2026-05-01); Suwannawach, PiyapanThis paper presents an improvement to the performance of a biquad oscillator, which is a recursive oscillator known for its excellent long-term stability. However, a significant limitation is that the oscillation frequency cannot be changed while the system is operating. Directly changing the frequency during operation causes the amplitude of the generated signal to vary significantly, either increasing or decreasing. A zero-input response analysis is used to understand the cause of this problem and to develop a solution that allows the amplitude of the generated signal to remain constant even when the oscillation frequency is changed during operation. In addition, this paper presents a method for controlling the phase of the generated signal by using a 1st-order IIR phase shifter structure. The proposed structure is specifically designed to allow the phase of the signal at the oscillation frequency to be adjusted continuously and independently of the frequency parameter. This integrated oscillator enables real-time, independent control of both signal frequency and phase without amplitude drift, making it suitable for applications requiring precise and dynamic signal synthesis. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Embedded Hardware Implementation of Noise Gate on STM32 Processor Using MATLAB/Simulink(2025-01-01) - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Evaluation of Multi-Bit Input Logic Blocks in RTL-Designed FPGA Architecture: A Framework for FPGA and ASIC Integration(2025-01-01); This paper explores the evaluation and optimization of multi-bit input logic blocks (LBs) within RTL-designed FPGA architectures. Traditional FPGA designs face limitations in power consumption, delay, and area due to the constraints of reconfigurable circuits. The proposed architecture leverages RTL-level design capabilities to address these challenges and enables the co-design of FPGAs and ASICs. The authors evaluate the performance of 8-bit, 16-bit, and 32-bit input LBs in terms of delay, area, and synthesis feasibility. The results demonstrate that 8-bit input LBs achieve a delay of 0.68 ns with an area of 2202.48 μm<sup>2</sup>, outperforming multi-stage smaller LBs. Although 16-bit input LBs show potential for delay reduction, their synthesis demands significant time and results in a large area footprint, rendering them impractical. Synthesis of 32-bit input LBs was not feasible due to current tool limitations. These findings highlight the effectiveness of 8-bit input LBs for pattern matching tasks and emphasize the importance of application-specific optimization. The fixed routing feature of RTL-designed FPGAs facilitates the development of efficient, customizable designs tailored to specific workloads. This work contributes to the advancement of FPGA architectures, offering insights for future research on larger input LBs and their integration into high-performance applications. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Application-Optimized FPGAs Design Using RTL-Designed FPGAs Architectures(2025-01-01); RTL-Designed Field-Programmable Gate Arrays (FPGAs) can describe FPGA functionality using Hardware Description Languages (HDLs), which means they can be easily customized to configure the FPGA. In conventional FPGAs, switches are used for routing control, making it impossible to design them using HDLs. This study leverages the customizable nature of RTL-Designed FPGAs to explore the optimal configuration of FPGAs for packet processing in computer networks. It demonstrates that a 4-input Look-Up Table (LUT) is superior to a 3-input LUT in terms of throughput and reveals that, as the number of LUT inputs increases, having 5 routing paths is more optimal than 4. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Amplitude Stabilization of Frequency-Tunable Biquad Digital Oscillator Using Zero-Input Response Analysis(2025-01-01);