Moungnoul, Phichet
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Preferred name
Moungnoul, Phichet
Alternative Name
Moungnoul, P.
Main Affiliation
Email
phichet.mo@kmitl.ac.th
55 results
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Item type:Publication, Pilot Flight Data Processing System for Airline Management(2023-01-01)This paper presents the development of a pilot flight performance analysis system for airline management designed to show the performance of an aircraft. A system that brings flight data from aircraft then decode to find the relevant parameters. After that, the parameters were analyzed the results of the pilot's flight performance. The results to be displayed by showing the measurement tool then take the parameters obtained to display in a flight simulation. In order to display the event that needs to be monitored by the measurement tool. The flight response caused by the aircraft or operators themselves can be find flaws in the pilot's flight performance. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Packet filtering circuits for smart phones(2012-12-01); Fukase, Masa AkiSecurity measures for smart phones are important. Anti-virus software for smart phones can be used and the process consumes CPU resources. The CPUs of them are powerless CPU for an embedded system and those operations consume battery power. In this paper, the authors propose packet filtering circuits for smart phones. The packet filtering circuits are a firewall. Using the firewall is a means to protect smart phones from computer viruses and unauthorized access. In addition, they are used to control the power consumption and to reduce of detecting units for unauthorized access. The features of the circuits are to achieve those functions without reconstructing circuits. The operations of the circuits are verified by gate-level simulations. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, RCA on FPGAs designed by the RTL design methodology and wave-pipelined operation(2016-09-06); ; Higuchi, KohjiField-programmable gate arrays (FPGAs) are used in various systems that use reconfigurable function. Conventional FPGAs have been developed by a transistor-level description for minimizing routing delay. Although FPGAs developed by the register transfer level (RTL) design methodology provide various benefits to the designers of a system-on-a-chip (SoC), they have not been realized. Therefore, the authors have advanced their development. They should be shown to operate in a practical throughput. For this purpose, circuits on them need to be designed and evaluated. In this paper, a ripple-carry adder (RCA) is designed on them and the throughput of the RCA is evaluated. The throughput shows that it is applicable to network processors. In addition, a wave-pipelined operation without changing the RCA reveals that the problem of routing delay in the FPGAs developed by the RTL methodology is mitigated. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, A crossbar switch circuit design for reconfigurable wave-pipelined circuits(2014-01-01); This paper states crossbar switches which are used for the efficient design in reconfigurable wave-pipelined circuits. In the hardware- and host-based IPS (Intrusion Prevention System) which is used in mobile computing, reconfigurable circuits for intrusion detecting are implemented and their design requires techniques for highspeed and low-power operations. Wave-pipeline is a technique for realizing them. On the other hand, using it makes a problem that consumes a large amount of logic block in a conventional FPGA (Field-Programmable Gate Array). To solve this problem, the authors have developed a logic block for wave-pipelining. However, a crossbar switch for controlling the logic blocks to be used has not been developed. In this paper, the crossbar switches are developed in RTL (Register Transfer Level) and delay times, area and power are calculated. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, A detection method of web authentication problems for mobile devices corresponding to IEEE 802.11ac(2018-05-30); - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Fine-tuning of wave-pipelines on FPGAs developed by the RTL design(2015-08-17); A wave-pipeline is a design technique for achieving high-speed and low-power operations also in field-programmable gate arrays (FPGAs). It realizes pipeline operations by adjusting delay times. Implementation of fine-tuning of wave-pipelines is possible to further increase the throughput. However, in the FPGA, it is not able to be executed by the restriction on the structure. This paper proposes a fine-tuning method for the FPGA developed by the register-transfer level (RTL) design. Although the RTL design of the FPGA has various advantages, it is required for a high-speed design for a routing delay which is larger than that of a conventional FPGA. The method is timing adjustment using a connection block with the RTL design. Results of analysis of the connection block show that the seven stages of the delay adjustment are possible in the block. In addition, the block can be used for rough-tuning of delay times. It is the area of less than half of the logic block. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Load sharing technique for coexistence LTE-FDD and LTE-TDD(2019-07-01); Anunvrapong, PramoteMobile network Operator is implemented coexistence LTE-TDD and LTE-FDD network, this technique used to improve the system capacity. The adjacent cell interference or ACI caused by these coexisting networks, which affected to the network performance. This paper investigates the load sharing technique to optimal the capacity of coexistence LTE network. Results show 4:6 of FDD and TDD user ratio that give maximum system throughput and comparing with power allocation and guard band technique will describe in this paper. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, A 0.18 μm CMOS Gaussian monocycle pulse circuit design for UWB(2006-12-01); Miyanaga, YohikazuThis paper proposes a new method of monocycle pulse generation by generating the Gaussian pulse, and generate first derivative of the pulse to get a Scholtz's monocycle pulse. The simulation result of the generation is based on 0.18 μn CMOS technology which achieved using HSPICE (Level 49). The Gaussian pulse is generated by using CMOS inverter of which is applied the delay time to perform the Gaussian pulse. ©2006 IEEE. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Comparison between measurement and prediction propagation model for PCT system(2005-12-01); - Some of the metrics are blocked by yourconsent settings
Item type:Publication, CMOS D/A converter using current conveyor analogue switches(2017-01-18); This paper presents a new digital-to-analog (D/A) converter circuit using second-generation current conveyors (CCIIs) which works as analogue switches. In this case, CCII is worked as current conveyor analogue switch (CCAS). A bit stream of digital code is used to control the switch for obtaining the current level at the output terminal. Then, bits D/A converter can be obtained simply by parallel connecting of CCASs. The proposed structure is suitable for low power supply voltage. The simulation results are used to confirm the workability of the proposed structure.