Vichienchom, Kasin
Loading...
6 results
Now showing 1 - 6 of 6
- Some of the metrics are blocked by yourconsent settings
Item type:Publication, A multi-gigabit DLL-based CMOS PWM demodulator using delay vernier sampler(2010-07-30) ;Cheewasrirungraung, DanaiponA CMOS PWM demodulator for multi-gigabit data rate is described. It uses a DLL and a delay vernier sampler to demodulate PWM signal with periodic rising edges. The sampler utilizes delay vernier technique to achieve a very fine sampling resolution. The proposed circuit was designed using AMS 0.35μm process parameters. The 4-bit encoded PWM signal is used in simulation. Simulation results show that the circuit is capable of demodulate and recover data at a data rate of 3 Gbps. The demodulator dissipates 66 mW at 3.3 V supply voltage. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, A 0.5 volt rail-to-rail CMOS pseudo-differential OTA using simple feed-forward technique(2011-08-12) ;Suadet, Apirak ;Thongleam, Thawatchai; This paper presents a low voltage CMOS pseudo differential OTA using simple feed-forward technique. The circuit employs feed-forward technique to suppress the common-mode gain, and positive feedback to enhance the output impedance. The circuit is designed using 0.18 μm CMOS technology under 0.5 V supply. The simulation results show rail-to-rail input/output swing, achieved with low common-mode gain (-35 dB). The output swing of the circuit is 0.3 Vpp. The power dissipation of the circuit is 50 μW. © 2011 IEEE. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, A 1 GHz CMOS analog equalizer for perpendicular magnetic recording(2010-12-01) ;Meksiri, Sukarasut; Wilairat, DechaThis paper describes the design of a CMOS analog discrete-time equalizer for perpendicular magnetic recording (PMR) read channel. In this design the structure of analog FIR filter that places rotating switch matrix between DAC and multiplier has been proposed. It reduces an accumulative switching error in analog samples due to rotating switch matrix. A 7-tap filter circuit based on GPR2 target was designed and simulated using TSMC 0.18 μm CMOS process parameters. Simulation results show good agreement with the results of the system level simulation. At 1 GHz sampling frequency the equalizer dissipates 1.5 mW. ©2010 IEEE. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Piezoelectric microactuator testing using heat-assisted capacitance measurement(2016-09-06) ;Paikaw, Ekkachai; Pojprapai, SoodkhetA technique for testing a piezoelectric microactuator of a read/write head of hard disk drive (HDD) is described. The proposed technique is based on the measurement of an equivalent capacitance of the PZT thin-film ceramic. It exploits the temperature dependent characteristic of the PZT. By carefully heating the PZT element while measuring its capacitance, the variation of its capacitance value can be observed. This profile is used to distinguish between a non-defected and a defected PZT actuator. The technique was implemented using a 5-watt green laser as the heating source. Experimental results show that when test with a HDD head stack assembly which is composed of multiple PZT actuators connected in parallel, it can identify a failed PZT actuator within seconds. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Performance of Log-MAP algorithm for graph-based detections on the 2-D interference channel(2014-01-01) ;Sopon, Thanomsak; The read channel of magnetic recording system is affected by two-dimensional interference channel that is a combination of inter-symbol interference and inter-track interference. Inter-track interference is one of the biggest challenges in the high density magnetic recording systems and it can degrade the performance of the channels. In this work, we compare three variations of log-MAP algorithms for graph-based detectors in two-dimensional interference channels. The simulation results show the performance of the graph-based detector with the full log-MAP and extended log-MAP algorithms achieve the gains of about 0.1 and 0.05 dB at BER = 10<sup>-5</sup>, over the max approximation on bit patterned media recording system with the areal density 2.5 Tbits/in<sup>2</sup>. © 2014 IEEE.1 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Target and equalizer design for perpendicular magnetic recording at 1 Tb/in2(2008-12-01) ;Meksiri, Sukarasut ;Wangtaphan, SkawratThis paper described the design of generalized partial-response (GPR) target and its corresponding equalizer for perpendicular magnetic recording (PMR) read channel with jitter noise. In this design the readback signal model uses transition response that its parameter is calculated based on media properties and reader head geometry specifically designed for 1 Tb/in <sup>2</sup> areal density. The GPR targets with various lengths are designed using minimum mean-squared error (MMSE) approach. The simulation results show that the BER performance of the system degrades as the ratio of jitter noise power to total noise power increases. According to these results GPR2 with 7-tap equalizer offers the optimal tradeoff between system performance and circuit implementation. copyright © 2008 IEICE.1
