Phakphisut, Watid

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5G Channel Coding Tool: Learning and Performance Evaluation
(2023-01-01)
Mueadkhunthod, Krittiyaporn
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Wongsa, Anusorn
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Srisupha, Thanat
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Duangthong, Chatuporn
;
Puntsri, Kidsanapong
The 5G channel coding tool is presented to explain channel coding in 5G New Radio (NR). Our tool consists of six modules such as information generator, channel encoder, modulator, noise generator, demodulator, and channel decoder. The channel encoder and modulator are developed according to 3GPP TS 38.212 and 3GPP TS 38.211 technical specifications, respectively. The 5G channel coding tool provides a graphical user interface (GUI) in which users can study the block diagrams of downlink and uplink process. In addition, our 5G channel coding tool can be used to evaluate the bit error rate performance of 5G channel coding in additive white Gaussian noise (AWGN) and fading channels.
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Design of partition decoding for polar codes in 5G new radio
(2020-10-08)
Wongsa, Anusorn
;
Phakphisut, Watid
;
Min Myint, Lin Min
;
Supnithi, Pornchai
In this work, we consider partition decoding to diminish the required memory of polar codes in 5G new radio. We show that the suitable design of partition decoding for downlink and uplink control channels may differ. Moreover, the partitioning technique can reduce the computation complexity of polar decoder by limiting the number of codewords passed between partitions. We then propose to use the parity bits of interleaved CRC codes to select the codewords passed between partitions. The parity bits can help the partition decoding of which the codewords are verified. The simulation results show that the parity bits can improve the performance of partition decoding of polar codes in the downlink control channel of 5G new radio.
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Design and Implementation of Forward-Backward Processing Unit for LDPC Decoder
(2023-01-01)
Wongsa, Anusorn
;
Phakphisut, Watid
This paper presents an efficient scalable architecture of node processing in low-density parity-check decoder. The node processing unit is based on the forward-backward algorithm. The proposed design relies on the cyclic shifting operation of scalable vectors. The number of nodes can be simply scaled without an increase of operator. Our design supports run-time scalability with a low hardware resource and high maximum operating frequency. The result of FPGA-based synthesis shows that, for every 1 degree increase, the number of logic elements increases at near linear rate roughly 47 elements, as well as the number of registers linearly increases at 48 registers. The clock cycles also linearly increase by 2 clock cycles per degree.
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Interleaved CRC codes for polar codes with partitioned list decoding
(2021-05-19)
Wongsa, Anusorn
;
Myint, Lin Min Min
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Supnithi, Pornchai
;
Phakphisut, Watid
In this work, we propose an interleaved cyclic redundancy check (CRC) code for the partitioned successive cancellation list (PSCL) decoder of polar codes. Since the CRC bits are interleaved into each partition of the PSCL decoder, the CRC bit can be used to eliminate the unreliable codewords. We examine that the performances of the PSCL decoder are influenced by the first-row weight of the parity-check matrix of interleaved CRC code. Therefore, the parity-check matrix of interleaved CRC code must be constructed by minimizing the first-row weight. The simulation results show that the interleaved CRC with a smaller weight can provide better error-correcting performance than the interleaved CRC with a larger weight.
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Development of 5G Polar Experimental Kit
(2022-01-01)
Wongsa, Anusorn
;
Mueadkhunthod, Krittiyaporn
;
Phakphisut, Watid
;
Duangthong, Chatuporn
;
Puntsri, Kidsanapong
The 5G polar experimental kit is presented for learning polar codes in 5G new radio. The experimental kit is developed to demonstrate the eleven encoding processes of polar codes described in 3GPP TS 38.212 technical specification. The experimental kit provides a graphical user interface (GUI) which a user can provide any the input parameters defined in the 5G new radio. The experimental kit provides a software and a hardware for a 5G polar encoder. After the polar encoder in the software or the hardware are done, the encoding results will be displayed on the GUI along with their processes details.
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Development of High Efficient LDPC Encoder for Deep Space Applications
(2023-01-01)
Srisupha, Thanat
;
Wongsa, Anusorn
;
Duangthong, Chatuporn
;
Phakphisut, Watid
In this paper, we present the design and implementation of a high efficient low-density parity-check (LDPC) encoder for deep space applications. The proposed encoder utilizes the generator matrix of CCSDS LDPC codes to simplify the encoding process and reduces the complexity of hardware implementation. The proposed encoder has two types. The first type aims to design a low-complexity architecture and flexibility. The second type presents high throughput architecture, allowing the user to choose the appropriate type according to their usage condition. The results of FPGA synthesis show that the proposed LDPC encoders achieve flexibility, low complexity, and high throughput.

Phakphisut, Watid

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