Phakphisut, Watid
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Phakphisut, Watid
Alternative Name
Phakphisut, W.
Main Affiliation
Email
watid.ph@kmitl.ac.th
16 results
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Item type:Publication, Reliability Ratio-Based Serial Algorithm of LDPC Decoder for Turbo Equalization Schemes(2022-02-01); Serial decoding algorithms of low-density parity-check (LDPC) code converge efficiently with low errors. Previously, a serial decoding algorithm, named a shuffled belief-propagation (SBP), was applied in turbo equalization of bit-patterned magnetic recording (BPMR) systems. With the SBP algorithm, an LDPC decoder converged twice as fast as one using conventional BP algorithms. We further improved the convergence speed of SBP by updating the messages in an adaptive order, which played a flexible role throughout decoding. We proposed two adaptive-serial algorithms for LDPC codes in turbo equalization. One updated the messages using the extrinsic loglikelihood ratio (LLR) and the result of the parity-check equation checking. The second contained an additional rule that tracked the LLR sign changes in each iteration. Both algorithms converged faster and with lower bit error rates (BERs) than the SBP and previous adaptive-serial algorithms in a BPMR system with media noise. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Performance of the hybrid MLPNN based VE (h MLPNN-VE) for the nonlinear PMR channels(2018-05-01); This paper proposes a hybrid of multilayer perceptron neural network (MLPNN) and Volterra equalizer (VE) denoted hMLPNN-VE in nonlinear perpendicular magnetic recording (PMR) channels. The proposed detector integrates the nonlinear product terms of the delayed readback signals generated from the VE into the nonlinear processing of the MLPNN. The detection performance comparison is evaluated in terms of the tradeoff between the bit error rate (BER), complexity and reliability for a nonlinear Volterra channel at high normalized recording density. The proposed hMLPNN-VE outperforms MLPNN based equalizer (MLPNNE), VE and the conventional partial response maximum likelihood (PRML) detector. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, EXIT chart analysis of nonbinary protograph LDPC codes for partial response channels(2014-11-01); ; Low-density parity-check (LDPC) codes over finite fields GF(q) provide an error correction in the noisy partial response (PR) channels. The extrinsic information transfer (EXIT) chart can be used to predict the threshold decoding of protograph LDPC codes, however, previous works only consider the binary protograph LDPC codes in the PR channels. In this paper, we propose to perform the EXIT chart analysis on the nonbinary protograph LDPC codes for the PR channels. Unlike prior works, the actual extrinsic information of the channel detector is measured, then the extrinsic information to the variable nodes is generated with the measured statistics. Moreover, since the mutual information of the variable nodes depends on GF(q), we use the Monte Carlo method to approximate the mutual information. The analysis on the regular (2,4) code, regular (3,6) code, RA code, and AR3A code on the PR channels reveal that, for the PR1 channel, the RA code outperforms the others for q = 2, 4, and 8, but the regular (2,4) code is the best for q = 16 and 32. For the PR2 channel, the RA code is the best code for q = 2 and 4, but the regular (2,4) code is the best code for q > 4. The simulation of the codes for q = 4 and 16 are then used to confirm the theoretical results. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Corner-truncated patch antenna with parasitic elements and circular feed slot for S-band CubeSat applications(2025-12-01); Torrungrueng, DanaiThis study presents a corner-truncated patch antenna with symmetrically loaded parasitic elements and a circular feed slot designed for CubeSat S-band communication applications. The antenna design evolves through successive stages, integrating corner truncations, a slit-ring structure, and segment-circular parasitic patches to enhance impedance matching and polarization performance. In its final configuration, a dual-stacked arrangement with inter-substrate spacing and a vertical capacitive feed further improves current distribution symmetry and broadens the operational bandwidth. Parametric analysis validates the effectiveness of each antenna design refinement, demonstrating improvements in impedance bandwidth, axial ratio bandwidth, and gain performance. The fabricated prototype achieves a wide impedance bandwidth from 1.65 GHz to 2.70 GHz, fully encompassing the CubeSat uplink (2.025–2.110 GHz) and downlink (2.200–2.290 GHz) frequency ranges. It maintains an axial ratio below 3 dB across 1.97 GHz to 2.32 GHz, ensuring efficient circular polarization. Additionally, a stable gain of approximately 7.50 dBic at 2.025 GHz supports reliable communication with ground stations. The combination of compact structure, low profile, and wideband circular polarization makes the proposed antenna a promising candidate for CubeSat communication systems. The novelty of this research lies in the integration of a corner-truncated patch, symmetrically loaded segment-circular parasitic elements, and a circular slit-ring capacitive feed within a dual-stacked substrate configuration to achieve wideband circular polarization and stable unidirectional radiation. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Reduced Complexity Window Decoding of Spatially Coupled LDPC Codes for Magnetic Recording Systems(2018-11-01); Spatially coupled low-density parity-check (SC-LDPC) codes have emerged to possess capacity-approaching performance. The SC-LDPC codes can be decoded by a sliding window, therefore, the decoding latency and complexity of SC-LDPC codes are lower than those of underlying LDPC codes when the codeword length is very large. In this paper, the SC-LDPC decoder with the sliding window is employed in turbo equalization of magnetic recording systems. We examine the bit error rates (BERs) of the output of the sliding window during the iterative decoding, and then observe that the consecutive code blocks have approximately the same BERs. Herein, to reduce decoding complexity of SC-LDPC codes, the consecutive code blocks can be considered as the output of SC-LDPC codes. In addition, the non-uniform schedule update is adopted in the window decoding to avoid unnecessary updates within a window. The simulation results show that the proposed decoding algorithms applied in bit-patterned media magnetic recording systems can achieve a significant reduction in complexity compared to the traditional decoding without any loss in BER performance. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Serial belief propagation for the high-rate LDPC decoders and performances in the bit patterned media systems with media noise(2011-01-01); ; - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Spread-F prediction model for the equatorial Chumphon station, Thailand(2020-01-01); ; - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Integer programming-based non-uniform window decoding schedules for spatially coupled low-density parity-check codes(2022-10-01); Spatially coupled low-density parity-check (SC-LDPC) codes generally use a window decoding scheme, which is known to yield a near-optimal decoding, compared to full block decoding. Recently, a non-uniform schedule has been proposed to eliminate unnecessary updates of variable nodes within a window: this schedule is generated based on the behaviour of variable node updates analysed by density evolution. Here, the authors present a new non-uniform schedule based on integer programming, whereby the objective functions and constraints are derived from a protograph-based extrinsic information transfer chart. Our design is more flexible than the previous design, because the integer programming-based design allows reduction of update numbers and performance losses through the constraints function, whereas the previous design requires observation of variable node update behaviour. The authors report the performance of their designs of non-uniform schedules in additive white Gaussian noise (AWGN) and inter-symbol interference (ISI) channels. Particularly, in the ISI channel, the authors’ non-uniform schedules are designed with cooperative decoding between a Bahl-Cocke-Jelinek-Raviv (BCJR) detector and an SC-LDPC decoder. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Two-Dimensional Error Correction Code for Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) Caches(2022-09-01); Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) is an emerging nonvolatile memory (NVM) technology that can replace conventional cache memory in computer systems. STT-RAM has many desirable properties such as high writing and reading speed, non-volatility, and low power consumption. Since the cache requires a high speed of writing and reading speed, a single-error correction and double error detection (SEC-DED) are applicable to improve the reliability of the cache. However, the process variation and thermal fluctuation of STT-MRAM cause errors. For example, writing ‘1’ bits has more errors than writing ‘0’ bits. We then design the weight reduction code to reduce the error caused by writing ‘1’ bits. Moreover, the performance of an SEC-DED code is improved by constructing an SED-DED code as the product code. The simulation results demonstrate that the two-dimensional error correction code consisting of product code and weight reduction code is roughly 5:67×10<sup>-4</sup> lower than the SEC-DED code when the error rate of writing ‘1’ bits is equal to 6 ×10<sup>-3</sup>. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Efficient Design of Read Voltages and LDPC Codes in NAND Flash Memory Using Density Evolution(2023-01-01); Low-density parity-check (LDPC) codes play an important role in the reliability enhancement of commercial NAND flash memory. Unfortunately, due to the requirement of the reading speed of NAND flash memory, the LDPC decoder will not obtain precise soft information to achieve high error-correcting capability. In this work, we use a density evolution (DE) algorithm to reveal the decoding threshold of the LDPC decoder affected by the read voltages. We propose the efficient design of read voltages so that the LDPC decoder has the lowest decoding threshold. Therefore, this method can guarantee that the designed read voltages are suitable for a given LDPC code. Moreover, since we found that the designed read voltages are related to the structure of the LDPC code, the joint design of the read voltages and LDPC code is then proposed to achieve the capacity of NAND flash memory. The simulation results demonstrate that our proposed design significantly improves the frame error rate (FER) performance of NAND flash memory.