Kittitornkun, Surin

Preferred name

Kittitornkun, Surin

Alternative Name

Kittitornkun, S.

Main Affiliation

School of Engineering

surin.ki@kmitl.ac.th

Now showing 1 - 10 of 39

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Analysing and optimizing snphap using radix-2 computation and openmp
(2013-07-12)
Ranokphanuwat, Ratthaslip
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Rattanatranurak, Apisit
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Kittitornkun, Surin
;
Tongsima, Sissades
In this paper, the run time complexity of SNPHAP, which is a haplotype inference tool, is extensively examined. The analysis is based on our previous work in terms of profiling and run-time complexity function. To reduce the run time complexity and enhance its performance, a Radix-2 computation and OpenMP multithreading are applied. The optimized results are compared with both original and compiler optimized versions on an AMD A6-3650 Linux machine. Due to the Radix-2 technique, the complexity is drastically reduced. In addition, the theoretical Speedup is consistent with the experimental one. Furthermore, up to 1,303% Speedup is achievable as a result of OpenMP multithreading.
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Massively parallel cuckoo pattern matching applied for NIDS/NIPS
(2010-05-21)
Thinh, Tran Ngoc
;
Kittitornkun, Surin
This paper describes a Cuckoo-based Pattern Matching (CPM) engine based on a recently developed hashing algorithm called Cuckoo Hashing. We implement the improved parallel Cuckoo Hashing suitable for hardware-based multi-pattern matching with arbitrary length. CPM can rapidly update the static pattern set without reconfiguration while consuming the lowest amount of hardware. With the power of massively parallel processing, the speedup of CPM is up to 128X as compared with serial Cuckoo implementation. Compared to other hardware systems, CPM is far better in performance and saves 30% of the area. © 2010 IEEE.
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Predicting SET50 stock prices using CARIMA (Cross Correlation ARIMA)
(2016-02-08)
Wichaidit, Sornpon
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Kittitornkun, Surin
Investing in stocks is one of the most popular approaches for money investment. This paper aims to predict short-term stock prices of SET50 of Stock Exchange of Thailand (SET). The proposed method is called CARIMA (Cross Correlation Autoregressive Integrated Moving Average. The basic idea of CARIMA is to find the most highly correlated s tock t o predict the target one in addition to ARIMA predicted price. The results of CARIMA model yield better price trends (measured by 10-day correlation coefficient) while % MAEs (Mean Absolute Errors) are quite similar with those of ARIMA.
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VLSI Signal Processing
(2005-12-01)
Kittitornkun, Surin
;
Hu, Yu Hen
The field of very large scale integrated (VLSI) signal processing concerns the design and implementation of signal processing algorithms using application-specific VLSI architecture, including programmable digital signal processors and dedicated signal processors implemented with VLSI technology. This chapter surveys important developments in this field, including algorithm design, architecture development, and design methodology. It also emphasizes DSP algorithm to hardware synthesis and its hardware implementation. An implementation of a digital signal processing (DSP) algorithm consists of the computer program of that algorithm and the hardware on which the program is executed. A DSP algorithm can be expressed as an n-level nested Do-loop, a recurrent equation, and a data flow graph (DFG). Next, one of these representations gets synthesized to its hardware counter- part. The hardware architecture is not only driven by the algorithm representation but also the sampling rate of input/ output signals. Due to limited hardware resources, operations and data of a particular algorithm can be scheduled at the right time and assigned at the right execution unit basis provided that the precedence and semantics are preserved. For a high- throughput application such as image/video processing, synthesis of a regular network of processing elements (PEs) is discussed in detail. Eventually, implementation technology and tools of a particular architecture are surveyed. © 2005 Copyright © 2005 Elsevier Inc. All rights reserved.
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Parallel Partition and Merge QuickSort (PPMQSort) on Multicore CPUs
(2016-03-01)
Ranokphanuwat, Ratthaslip
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Kittitornkun, Surin
An explosive amount of data has tremendous impacts on sorting, searching, indexing, and so on. Sorting is one of the basic Computer Science problems needed to be fast and efficient to serve Big Data. This paper presents an efficient and scalable algorithm called Parallel Partition and Merge QuickSort (PPMQSort) running on any shared memory/multicore/multi-socket systems. Together with OpenMP 3.0 library, the PPMQSort is developed to be compatible and benchmarked with the fastest C/C++ Stdlib qsort(). The PPMQSort recursively divides an unsorted input array into partially sorted partitions up to Cutoff length using nested multithreading. Finally, those independent partitions are qsort() (conquered) such that no synchronizations are needed. The resulting Speedup of 12.29 (Formula presented.) on a dual-socket 8-core Xeon E5520 can be achieved for sorting random 200 M 32-bit integer data at 16 threads. With the same configuration, a 4-core AMD A6-3600 CPU (non-HyperThread) can reach up to 4.67 (Formula presented.) , a superlinear Speedup. It has been proved that the proposed PPMQSort can exploit all available cache levels and HyperThread CPU cores well thus utilizing up to 83 % and 96 % of CPU on E5520 and A6-3600, respectively.
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Applying Cuckoo Hashing for FPGA-based pattern matching in NIDS/NIPS
(2007-12-01)
Thinh, Tran Ngoc
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Kittitornkun, Surin
;
Tomiyama, Shigenori
Pattern matching for network intrusion/prevention detection requires extremely high throughput with frequent updates to support new attack patterns. Most of current hardware implementations have outstanding performance over software implementations. However, the requirement for dynamic update pattern set is still challenging for hardware researchers. This paper describes a novel FPGA-based pattern matching architecture using a recent hashing algorithm called Cuckoo Hashing. The proposed architecture features on-the-fly pattern updates without reconfiguration, more efficient hardware utilization, and higher performance. Through various algorithmic changes of Cuckoo Hashing, we can implement parallel pattern matching on SRAM-based FPGA. Our system can accommodate the latest Snort rule-set, an open source Network Intrusion Detection/Prevention System, and achieve the highest utilization in terms of SRAM per character and Logic Cells per character at 17 bits/character and 0.043 Logic Cells/character, respectively on major Xilinx Virtex architectures. Compared to others, ours is much more efficient than any other Xilinx FPGA architectures. © 2007 IEEE.
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A FPGA-based deep packet inspection engine for network intrusion detection system
(2012-10-02)
Thinh, Tran Ngoc
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Hieu, Tran Trung
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Dung, Van Quoc
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Kittitornkun, Surin
Pattern matching has became a bottleneck of software based Network Intrusion Detection System (NIDS) as the number of signature have recently increased dramatically. Many FPGA-based architectures for detecting malicious patterns have been proposed recently. However, these approaches have just considered matching pattern separately while more and more complex combination of several patterns are utilized to describe intrusion activities. In this paper we present our work which concentrates on multi-pattern signature and propose a FPGA-based deep packet inspection engine for NIDS. The system can support both static and dynamic patterns. We employ Snort signature set and realize our system on NetFPGA platform. The evaluation on real network environment shows that our system can maintain gigabit line rate throughput without dropping packets. © 2012 IEEE.
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Temporal behaviors of Top-10 malware download in 2010-2012
(2014-10-15)
Yukonhiatou, Chaxiong
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Kittitornkun, Surin
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Kikuchi, Hiroaki
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Sisaat, Khamphao
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Terada, Masato
Malware can be widely downloaded over the Internet by the bot-infected computers according to their botmaster in order to form a botnet and eventually to perform cyber attacks. This paper analyzes and summarizes the malware download behaviors of Top-10 malware based on 2010 CCC, 2011 CCC and 2012 IIJ MITF datasets. The datasets contain millions of download logs collected from several Honeypots located in Japan observing malware/bot traffic and activities. These log data have been processed and analyzed in terms of daily and hourly downloads based on our Top-10 processing algorithm. As a result, both daily and hourly download patterns in each year are quite different due to different malware families and spreading protocols.
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A multithreading methodology with OpenMP on multi-core CPUs: SNPHAP case study
(2011-08-12)
Ranok, Udom
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Kittitornkun, Surin
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Tongsima, Sissades
This paper presents a multithreading methodology for OpenMP library. The methodology can be applied to convert existing sequential and demanding programs to be multithreaded programs with OpenMP running on the Multi-core CPUs. In our experiments, we apply this methodology to SNPHAP, which is one of the best haplotype inference bioinformatics program in terms of speed. The results show that our significant achievement is the maximum Speedup 316% for Intel Xeon E5405 (8-core 2.0 GHz) and 410% for Intel Xeon E5520 (8-Core with HyperThreading 2.66GHz) faster than its own sequential version. © 2011 IEEE.
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FPGA-based cuckoo hashing for pattern matching in NIDS/NIPS
(2007-01-01)
Tran, Thinh Ngoc
;
Kittitornkun, Surin
Pattern matching for network intrusion/prevention detection demands exceptionally high throughput with recent updates to support new attack patterns. This paper describes a novel FPGA-based pattern matching architecture using a recent hashing algorithm called Cuckoo Hashing. The proposed architecture features on-the-fly pattern updates without reconfiguration, more efficient hardware utilization, and higher throughput. Through various algorithmic changes of Cuckoo Hashing, we can implement parallel pattern matching on SRAM-based FPGA. Our system can accommodate the newest Snort rule-set, an open source Network Intrusion Detection/Prevention System, and achieve the highest utilization in terms of SRAM per character and Logic Cells per character at 15.63 bits/character and 0.033 Logic Cells/character, respectively on major Xilinx Virtex FPGA architectures. Compared to others, ours is more efficient than any other Xilinx FPGA architectures. © Springer-Verlag Berlin Heidelberg 2007.
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Kittitornkun, Surin

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