Kittitornkun, Surin
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Preferred name
Kittitornkun, Surin
Alternative Name
Kittitornkun, S.
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Email
surin.ki@kmitl.ac.th
16 results
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Item type:Publication, Applying Cuckoo Hashing for FPGA-based pattern matching in NIDS/NIPS(2007-12-01); Tomiyama, ShigenoriPattern matching for network intrusion/prevention detection requires extremely high throughput with frequent updates to support new attack patterns. Most of current hardware implementations have outstanding performance over software implementations. However, the requirement for dynamic update pattern set is still challenging for hardware researchers. This paper describes a novel FPGA-based pattern matching architecture using a recent hashing algorithm called Cuckoo Hashing. The proposed architecture features on-the-fly pattern updates without reconfiguration, more efficient hardware utilization, and higher performance. Through various algorithmic changes of Cuckoo Hashing, we can implement parallel pattern matching on SRAM-based FPGA. Our system can accommodate the latest Snort rule-set, an open source Network Intrusion Detection/Prevention System, and achieve the highest utilization in terms of SRAM per character and Logic Cells per character at 17 bits/character and 0.043 Logic Cells/character, respectively on major Xilinx Virtex architectures. Compared to others, ours is much more efficient than any other Xilinx FPGA architectures. © 2007 IEEE. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Systolic array for string matching in NIDS(2007-12-01) - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Power optimization for mobile MPEG-4 video decoder(2005-12-01) - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Low energy optimization for MPEG-4 video encoder on ARM-based mobile phones(2006-11-02) - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Supersystolic arrays on large-scale FPGA structures(2003-07-14); Hu, Yu HenA system-on-a-chip with reconfigurable hardware such as SRAM-based FPGAs is evidently suitable for several applications on wearable computers. However, interconnect delay of current stateof-the-art FPGAs dominates the logic delay with relatively high power consumption. To counterbalance these two problems while maintaining desirable performance, voltage downscaling and fine-grained pipelining have been suggested. In this paper, we propose a pipelining methodology to utilize intra-iteration parallelism of a systolic-like array realized in a multimillion-gate FPGA. This results in not only enhanced throughput but also much higher hardware utilization. Thus, we call it the supersystolic array. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, MPEG-4 video mobile uplink caching algorithm(2008-10-06) - Some of the metrics are blocked by yourconsent settings
Item type:Publication, VLSI Signal Processing(2004-01-01); Hu, Yu HenThe field of very large scale integrated (VLSI) signal processing concerns the design and implementation of signal processing algorithms using application-specific VLSI architecture, including programmable digital signal processors and dedicated signal processors implemented with VLSI technology. This chapter surveys important developments in this field, including algorithm design, architecture development, and design methodology. It also emphasizes DSP algorithm to hardware synthesis and its hardware implementation. An implementation of a digital signal processing (DSP) algorithm consists of the computer program of that algorithm and the hardware on which the program is executed. A DSP algorithm can be expressed as an n-level nested Do-loop, a recurrent equation, and a data flow graph (DFG). Next, one of these representations gets synthesized to its hardware counter- part. The hardware architecture is not only driven by the algorithm representation but also the sampling rate of input/ output signals. Due to limited hardware resources, operations and data of a particular algorithm can be scheduled at the right time and assigned at the right execution unit basis provided that the precedence and semantics are preserved. For a high- throughput application such as image/video processing, synthesis of a regular network of processing elements (PEs) is discussed in detail. Eventually, implementation technology and tools of a particular architecture are surveyed. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Energy optimization for mobile MPEG-4 video decoder(2005-01-01) - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Optimizing RSA encryption for ARM microprocessor(2008-10-06) - Some of the metrics are blocked by yourconsent settings
Item type:Publication, PAMELA: Pattern matching engine with Limited-time updAte for NIDS/NIPS(2009-01-01); Tomiyama, ShigenoriSeveral hardware-based pattern matching engines for network intrusion/prevention detection systems (NIDS/NIPSs) can achieve high throughput with less hardware resources. However, their flexibility to update new patterns is limited and still challenging. This paper describes a PAttern Matching Engine with Limited-time updAte (PAMELA) engine using a recently proposed hashing algorithm called Cuckoo Hashing. PAMELA features on-the-fly pattern updates without reconfiguration, more efficient hardware utilization, and higher performance compared with other works. First, we implement the improved parallel exact pattern matching with arbitrary length based on Cuckoo Hashing and linkedlist technique. Second, while PAMELA is being updated with new attack patterns, both stack and FIFO are utilized to bound insertion time due to the drawback of Cuckoo Hashing and to avoid interruption of input data stream. Third, we extend the system for multi-character processing to achieve higher throughput. Our engine can accommodate the latest Snort rule-set, an open source NIDS/NIPS, and achieve the throughput up to 8.8 Gigabit per second while consuming the lowest amount of hardware. Compared to other approaches, ours is far more efficient than any other implemented on Xilinx FPGA architectures. Copyright © 2009 The Institute of Electronics, Information and Communication Engineers.