Kittitornkun, Surin
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Preferred name
Kittitornkun, Surin
Alternative Name
Kittitornkun, S.
Main Affiliation
Email
surin.ki@kmitl.ac.th
31 results
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Item type:Publication, Applying Cuckoo Hashing for FPGA-based pattern matching in NIDS/NIPS(2007-12-01); Tomiyama, ShigenoriPattern matching for network intrusion/prevention detection requires extremely high throughput with frequent updates to support new attack patterns. Most of current hardware implementations have outstanding performance over software implementations. However, the requirement for dynamic update pattern set is still challenging for hardware researchers. This paper describes a novel FPGA-based pattern matching architecture using a recent hashing algorithm called Cuckoo Hashing. The proposed architecture features on-the-fly pattern updates without reconfiguration, more efficient hardware utilization, and higher performance. Through various algorithmic changes of Cuckoo Hashing, we can implement parallel pattern matching on SRAM-based FPGA. Our system can accommodate the latest Snort rule-set, an open source Network Intrusion Detection/Prevention System, and achieve the highest utilization in terms of SRAM per character and Logic Cells per character at 17 bits/character and 0.043 Logic Cells/character, respectively on major Xilinx Virtex architectures. Compared to others, ours is much more efficient than any other Xilinx FPGA architectures. © 2007 IEEE. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, A FPGA-based deep packet inspection engine for network intrusion detection system(2012-10-02) - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Systolic array for string matching in NIDS(2007-12-01) - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Performance analysis & improvement of SNPHAP on Multi-core CPUs(2013-09-02); Tongsima, SissadesIn this paper, we attempt to analyse this highly computational problem by parallelizing a haplotype inference algorithm, called SNPHAP. The analysis is based on both the orignal (sequential) algorithm and its corresponding run time complexity in Big-O notations. Then, we improve its performance using OpenMP 3.0 and test on a 4-core Intel Core i7-2600 (Hyper-Threading), an 8-core Intel XeonE5405, an 8-core Intel Xeon E5520 (Hyper-Threading) and a 32-core AMD Opteron 8356 Linux machines. The achievements in terms of maximum speedups are 260%, 316%, 410% and 488%, respectively. The factors that affect the speedup of SNPHAP are the specific parallelized code fraction, the suitable OpenMP constructs, the number of physical cores, the sizes of cache memories within/among CPU cores, the clock frequency and finally the memory technology. © 2013 IEEE. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Geographical visualization of malware download for anomaly detection(2012-11-06) - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Power optimization for mobile MPEG-4 video decoder(2005-12-01) - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Parallel hybrid dual pivot sorting algorithm(2017-11-03) - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Low energy optimization for MPEG-4 video encoder on ARM-based mobile phones(2006-11-02) - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Supersystolic arrays on large-scale FPGA structures(2003-07-14); Hu, Yu HenA system-on-a-chip with reconfigurable hardware such as SRAM-based FPGAs is evidently suitable for several applications on wearable computers. However, interconnect delay of current stateof-the-art FPGAs dominates the logic delay with relatively high power consumption. To counterbalance these two problems while maintaining desirable performance, voltage downscaling and fine-grained pipelining have been suggested. In this paper, we propose a pipelining methodology to utilize intra-iteration parallelism of a systolic-like array realized in a multimillion-gate FPGA. This results in not only enhanced throughput but also much higher hardware utilization. Thus, we call it the supersystolic array. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, TCP reassembly for signature-based network intrusion detection systems(2012-10-02); Vu, Tran HuyRapid development of network makes it a very important and vulnerable part of every field of life. Many intrusion detection systems are developed to protect the network using signature-based matching technique. For connection oriented protocols, such as Transmission Control Protocol, the data should be reassembled before being scanned by the matching engine. Several techniques are introduced to reassemble TCP packets on FPGA. However, they have some disadvantages such as inefficient memory, unscalable system, and unsupported complex TCP connections. In this paper, we propose a multi-linked-list approach and a combination of edge buffering scheme for TCP reassembly, which helps detecting cross packets intrusion signatures. Our architecture not only supports TCP connections with up to 4 concurrent holes, but also uses memory more efficiently than others. The experimental results show that our system can hold about 256K connections simultaneously and support up to 46K out-of-sequence connections with only 64MB DRAM. © 2012 IEEE.