Performance estimates of an embedded CPU for high-speed packet processing

Abstract

This paper states an embedded CPU performance required for processing packets at a continuous throughput of 1 Gbps. And the out-of-order execution of packets is proposed for processing a variety of packet frame size in the CPU performance. Despite the requirement of high-speed network connections in embedded devices and mobile devices, it is not realized that an embedded CPU capable of high-speed packet processing with low-power operations. In this paper, the authors estimate operating frequencies for processing packets at a continuous throughput of 1 Gbps using a MIPS architecture which is widely used for network devices or embedded systems today. Then, the cases that must be processed with a high-spec CPU is revealed, the solution is proposed. When the frequency of 1.0 GHz and 64-bit registers are used, the CPU usage is 11.0 %. © 2014 IEEE.