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High-speed and low-power ECL circuits design based on BiCMOS technology
Author(s)
Date Issued
December 1, 1998
Type
Article
Abstract
This paper proposes the high speed digital circuit design techniques in order to obtain the small circuit area and low power dissipation. The proposed techniques are a developed feedback controlled current source-active pull down-emitter coupled logic (FCCS-APD-ECL) and a current mirror biasing circuit of gated diode-active pull down-emitter coupled logic (GD-APD-ECL). The technique of FCCS-APD-ECL is used to obtain small circuit chip area and low power dissipation, the technique of GD-APD-ECL is used to obtain the high speed of the circuit. Both proposed circuits performances are carried out.
Citation
IEEE Asia Pacific Conference on Circuits and Systems Proceedings, 41-44, 1998