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A DXCCII-based four-quadrant multiplier
Author(s)
Date Issued
August 28, 2013
Type
Conference Paper
Abstract
This paper presents a four-quadrant analog multiplier using dual-X second-generation current conveyors (DXCCIIs). The proposed multiplier employs only two DXCCIIs and eight MOS transistors operating in saturation region, which is ideal for monolithic implementation. The use of MOS devices operating in saturation region offers high-frequency capability of the circuit. PSPICE simulators using 0.35 μm TSMC CMOS process are used to validate the workability of the circuit. Simulation results show that the circuit has a -3dB bandwidth of 450 MHz, 1.59 % total harmonic distortion for the input current 200 mVP-P. © 2013 IEEE.
Citation
Proceedings of the 2013 IEEE 7th International Power Engineering and Optimization Conference Peoco 2013, 738-741, 2013