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Design high speed and low power hybrid full adder circuit
Author(s)
Lueangsongchai, Sathaporn
Date Issued
December 24, 2018
Type
Conference Paper
Abstract
This paper presents 1-bit hybrid full adder cells circuit scheme that high speed and low power consumption. This Full adder cells circuit is designed utilization of XOR gate, XNOR gate, pass logic gate and transmission gate. Result of simulation by HSPICE program based on 16 nm CMOS technology with 0.9V power supply voltage and maximum frequency at 8GHz.
Citation
Iscit 2018 18th International Symposium on Communication and Information Technology, 22-25, 2018