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Dual translinear analog multiplier
Author(s)
Date Issued
December 1, 2001
Type
Conference Paper
Abstract
In this article, an integrable circuit technique for implementing an analog multiplier is presented. The realization method makes use of the dual translinear characteristic of bipolar junction transistors. The proposed circuit achieves a wide dynamic range and high accuracy. Simulation results demonstrating the characteristic of the proposed circuit are included.
Citation
International Symposium on IC Technology Systems and Applications, 9, 98-101, 2001