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High-speed low input impedance CMOS current comparator
Author(s)
Khucharoensin, Surachet
Date Issued
January 1, 2005
Type
Conference Paper
Abstract
A simple high-speed low input impedance CMOS current comparator is presented. The circuit uses improved Wilson current-mirror to perform subtraction. Negative feedback is employed to reduce the input impedance of the circuit. HSPICE is used to verify the circuit performance with standard 0.5 μm CMOS technology. Simulation results demonstrate propagation delay of 1.02ns, average power consumption of 0.9 mW, and input impedance of 137 Ω for ±0.1 μA input current at the supply voltage of 3V. Copyright © 2005 The Institute of Electronics, Information and Communication Engineers.
Citation
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, E88-A(6), 1549-1553, 2005