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A robust high-speed low input impedance CMOS current comparator
Author(s)
Khucharoensin, Surachet
Date Issued
December 1, 2008
Type
Article
Abstract
In this paper, a robust high-speed low input impedance CMOS current comparator is proposed. The front end of the comparator uses the modified Wilson current-mirror and diode-connected transistors to perform a current subtraction and current to voltage conversion simultaneously. The circuit is immune to the process variation and has low input impedances. HSPICE is used to verify the circuit performance with a 0.5 μm CMOS technology. The simulation results show the propagation delay of 1.67 ns, input impedances of 123 Ω, and 126 Ω, and average power dissipation of 0.63 mW for ± 0.1 μA input current under the supply voltage of 3 V. © 2008 World Scientific Publishing Company.
Citation
Journal of Circuits Systems and Computers, 17(6), 1139-1149, 2008