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1.5-V CMOS current multiplier/divider
Author(s)
Satansup, Jetsdaporn
Date Issued
June 1, 2018
Type
Article
Abstract
A circuit technique for designing a compact low-voltage current-mode multiplier/divider circuit in CMOS technology is presented. It is based on the use of a compact current quadratic cell able to operate at low supply voltage. The proposed circuit is designed and simulated for implementing in TSMC 0.25-μm CMOS technology with a single supply voltage of 1.5 V. Simulation results using PSPICE, accurately agreement with theoretical ones, have been provided, and also demonstrate a maximum linearity error of 1.5%, a THD less than 2% at 100 MHz, a total power consumption of 508 μW, and -3dB small-signal frequency of about 245 MHz.
Citation
International Journal of Electrical and Computer Engineering, 8(3), 1478-1487, 2018