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Efficient Processing Time with Carry-lookahead Adder Memristor Rationed Logic
Author(s)
Yamtim, Suparlerk
Date Issued
January 1, 2023
Type
Conference Paper
Abstract
This paper presents a novel approach to the design of full adder circuits, leveraging the unique properties of memristors and CMOS logic in a hybrid system. This paper explores the design and operation of memristor-based logic gates, including AND, OR, NAND, and NOR gates, realized through CMOS inverters. This paper further proposes a full adder circuit using Hybrid Memristor-CMOS logic and a carry look-Ahead adder (CLA). Our simulations demonstrate that the proposed full adder circuit outperforms traditional RCA-based circuits in terms of speed. This work contributes to the ongoing discourse in digital electronics, offering fresh perspectives and potential solutions to existing challenges, and hope it will inspire further research in the field of memristor-based digital electronics.
Citation
2023 9th International Conference on Engineering Applied Sciences and Technology Iceast 2023 Proceeding, 123-126, 2023