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0.75-V four-quadrant current multiplier using floating gate-MOS transistors
Author(s)
Chanwutitum, Jirasak
Date Issued
October 15, 2014
Type
Conference Paper
Abstract
This paper presents a new ultra-low-voltage current-mode four-quadrant analog multiplier. A floating-gate technique is used to provide operating at a supply voltage of 0.75 V for the proposed circuit. PSPICE simulators using 0.18 μm TSMC CMOS process are used to show the workability of the multiplier. Simulation results show that the circuit has a linearity error of 1.5 % for the input current 8 μA, total harmonic distortion of 0.96 % for the input current 8 μApeak and quiescent power consumption of 19.9 μW.
Citation
2014 International Electrical Engineering Congress Ieecon 2014, 2014