31.3 nW, 0.5 V Bulk-Driven OTA for Biosignal Processing

Abstract

This paper presents a new extremely low-voltage low-power bulk-driven (BD) operational transconductance amplifier (OTA) realized for low frequency biosignal processing. The CMOS structure of the OTA utilizes bulk-driven and self-cascode techniques in the subthreshold region, supporting the operation with the supply voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm {DD}}$ </tex-math></inline-formula> ) as the threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm {TH}}$ </tex-math></inline-formula> ) of a single MOS transistor, i.e., <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm {DD}}$ </tex-math></inline-formula> = <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm {TH}}$ </tex-math></inline-formula> = 0.5 V, while offering nano power consumption (31.3 nW for 15 nA nominal setting current). Using the extremely low-voltage and low-power OTA in biosignal processing enables extending the lifetime of applications that are powered by battery or energy harvesting sources. The OTA has a 54.7 dB low frequency gain, 6.18 kHz gain bandwidth and 75° phase margin at 15 pF load capacitance. The proposed OTA has been used to realize a bandpass filter (BPF) with adjustable gain for electrocardiogram (ECG) signal processing. The higher cutoff frequency of the BPF is adjustable electronically by a setting current and the BPF’s gain can be adjusted by capacitors value. The total harmonic distortion (THD) of the BPF is −53.56 dB, the input integrated input-referred voltage noise is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$17.9 \mu \text{V}_{\mathrm {rms}}$ </tex-math></inline-formula> , the common mode rejection ratio (CMRR) is 75 dB and the power supply rejection ratio (PSRR) is 87.7 dB. The BPF was designed in the Cadence program using <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18 \mu \text{m}$ </tex-math></inline-formula> CMOS technology from TSMC. The simulation results agree with the presented theory.