Design and Implementation of Forward-Backward Processing Unit for LDPC Decoder

Abstract

This paper presents an efficient scalable architecture of node processing in low-density parity-check decoder. The node processing unit is based on the forward-backward algorithm. The proposed design relies on the cyclic shifting operation of scalable vectors. The number of nodes can be simply scaled without an increase of operator. Our design supports run-time scalability with a low hardware resource and high maximum operating frequency. The result of FPGA-based synthesis shows that, for every 1 degree increase, the number of logic elements increases at near linear rate roughly 47 elements, as well as the number of registers linearly increases at 48 registers. The clock cycles also linearly increase by 2 clock cycles per degree.