Dual symbol processing for MQ arithmetic coder in JPEG2000

Abstract

In this paper, a design of a dual symbol processor for arithmetic coder architecture implemented on FPGA is proposed. Usually, the regular operation of the MQ-Coder is sequential, which can process only one symbol at a time. However, the bit-plane coding can generate more than one symbol per clock cycle. Consequently, the coding speed will be limited and bottlenecked at the interface between the output of the bit-plane coding and the input of the MQ-Coder. Therefore, the proposed MQ-Coder architecture is designed to process two symbols for each clock cycle. The success comes from the proposed prediction process of the upper bound value and the index value. As a result, the proposed arithmetic coder architecture can process with the speed greater than 100 MHz with the throughput greater than 60 Msymbols/sec. © 2008 IEEE.