The effects of geometrical capacitance components of LOCOS diode in VLSI

Abstract

The effects of geometrical capacitance components of LOCal Oxidation of Silicon (LOCOS) diode in Very Large Scale Integrated circuit (VLSI) are proposed. For the correct circuit model simulation, the model of the device must be accurate and consistence with the SPICE models. The rectangular structure (L=400 μm, W=200 μm), the multi-fringe structure 1 (L=400 μm, W=4 μm, no. strips =50) and the multi-fringe structure 2 (L= S μm, W= Sμm, no. sample =1200) have been designed. These extraction methodologies show the area capacitance component, the peripheral capacitance component and the corner capacitance component at the field oxide side. The BSIM 3v3 junction capacitance models are proposed also. The comparison is made to check the accuracy of the parameter models. The results showed a low level error.