FPGA implementation of QR decomposition using MGS algorithm

Boonpoonga, Akkarat; Janyavilas, Sompop; Sirisuk, Phaophak; Krairiksh, Monai

doi:10.1007/978-3-642-12133-3_39

FPGA implementation of QR decomposition using MGS algorithm

Author(s)

Boonpoonga, Akkarat

Janyavilas, Sompop

Sirisuk, Phaophak

Krairiksh, Monai

Date Issued

April 29, 2010

Type

Conference Paper

DOI

10.1007/978-3-642-12133-3_39

Abstract

FPGA implementation of MGS-QRD is presented in this paper. Mapping conventional QR triangular array of (2m ²+3m+1) cells onto a linear architecture of m+1 cells is employed to reduce the number of required QR processors. The architecture for MGS-QRD implementation is discussed, including the structure of a boundary cell (BC) and internal cell (IC). A divider in BC is modified as a Look-Up Table (LUT) and multiplier. The multiplier divided from the divider can be accomplished by sharing it with another multiplier to reduce the resource for BC implementation. Furthermore, the conventional complex multiplication in IC is also modified with three multipliers and four adders. The designed architecture based on discrete mapping of MGS-QRD is implemented to examine FPGA resource utilization. The implementation results show the FPGA performance and resource utilization of MGS-QRD. © 2010 Springer-Verlag.

Citation

Lecture Notes in Computer Science Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics, 5992 LNCS, 394-399, 2010