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A CMOS log-antilog current multiplier/divider circuit using DDCC
Author(s)
Date Issued
December 1, 2011
Type
Conference Paper
Abstract
This paper presents a new one-quadrant analog log-antilog multiplier/divider using only one differential different current conveyor and four diodes. The proposed circuit features low circuit complexity, very suitable for integrated circuit implementation and excellent temperature stability. Simulation results show performance of the circuit and confirm the validity of the proposed design technique. © 2011 IEEE.
Citation
IEEE Region 10 Annual International Conference Proceedings TENCON, 634-637, 2011