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Low power CMOS full adder cells
Author(s)
Date Issued
October 2, 2012
Type
Conference Paper
Abstract
This paper presents low power CMOS full adder cells. The full adder cells are utilization to low power by using XOR and XNOR gate architectures with pass transistor logic and transmission gate. All simulation results have been carried out by using HSPICE program simulator based on 22 nm CMOS technology at 1.2 V supply voltages. The operating frequency is 250 MHz. In comparison with other 1 bit adder cells, simulation results show that have used low power consumption and power delay product of SUM and C OUT. © 2012 IEEE.
Citation
2012 9th International Conference on Electrical Engineering Electronics Computer Telecommunications and Information Technology Ecti Con 2012, 2012