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Low-voltage low-power bulk-driven analog median filter
Author(s)
Date Issued
May 1, 2016
Type
Article
Abstract
This paper presents low-voltage (LV) low-power (LP) voltage-mode analog median filter based on winner-take-all (WTA) and loser-take-all (LTA) circuits. The LTA and WTA CMOS structures are performed utilizing bulk-driven (BD) MOS transistor (MOST) technique, enabling circuits to operate under low supply voltage of only ±0.25 V and consume extremely low-power in micro range. In addition to the simple topology of the proposed circuits, they provide high accuracy. Moreover, the common mode voltage range is near rail-to-rail. Eventually, to verify the functionality of the proposed circuits, the simulation results are carried out in Cadence environment using triple-well 0.18 μm CMOS process.
Citation
AEU International Journal of Electronics and Communications, 70(5), 698-706, 2016