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Analog median filtering circuit using CMOS three-input max/min cell
Author(s)
Date Issued
June 8, 2018
Type
Conference Paper
Abstract
This paper presents a current-mode design technique for complementary metal oxide semiconductor (CMOS) implementation of an analog median filtering circuit for real-time signal processing. The proposed three-input median filtering circuit consists of three-input maximum/ minimum (max/min) cell, dual-output current mirrors, and current summation. The max/min cell used is based on an existing multiple-input max/min circuit for simultaneously determining the maximum and minimum values of input signals to overcome the limitations of tree realization by using two-input max/min selectors. Additionally, transistors used in the max/min cell are biased at the edge of conduction to minimize corner errors. PSPICE simulation results are given to verify the operation of the proposed median filtering circuit.
Citation
2018 3rd International Conference on Control and Robotics Engineering Iccre 2018, 155-159, 2018