Robust high-speed low input impedance CMOS current comparator

Khucharoensin, Surachet; Kasemsuwan, Varakorn

Robust high-speed low input impedance CMOS current comparator

Author(s)

Khucharoensin, Surachet

Kasemsuwan, Varakorn

Date Issued

December 1, 2004

Type

Conference Paper

Abstract

In this paper, a robust high speed low input impedance CMOS current comparator is proposed. The circuit uses modified Wilson current-mirror to perform a current subtraction. Negative feedback is employed to reduce input impedances of the circuit. The diode connected transistors of the same type(NMOS) are used at the output making the circuit immune to the process variation. HSPICE is used to verify the circuit performance and the results show the propagation delay of 1.67 nsec with an average power dissipation of 0.63 mW using a standard 0.5μm CMOS technology for an input current of ±0.1μA at the supply voltage of 3V. The input impedances of the proposed current comparator are 123 ω and 126 ω while the maximum output voltage variation is only 1.9%.

Citation

Midwest Symposium on Circuits and Systems, 1, I93-I96, 2004