Analog operation in CMOS latch circuit for reducing dynamic power dissipation

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dc.contributor.authorK. Dejhan
dc.contributor.authorF. Cheevasuvit
dc.contributor.authorV. Tipsuwanporn
dc.contributor.authorT. Trisuwannawat
dc.contributor.authorE. Prommas
dc.date.accessioned2025-07-21T05:47:32Z
dc.date.issued2003-01-02
dc.identifier.doi10.1109/mwscas.1992.271266
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/418
dc.subjectClock rate
dc.subject.classificationAnalog and Mixed-Signal Circuit Design
dc.titleAnalog operation in CMOS latch circuit for reducing dynamic power dissipation
dc.typeArticle

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