Evaluation of Multi-Bit Input Logic Blocks in RTL-Designed FPGA Architecture: A Framework for FPGA and ASIC Integration

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dc.contributor.authorTomoaki Sato
dc.contributor.authorAnyu Murakami
dc.contributor.authorSorawat Chivapreecha
dc.contributor.authorPhichet Moungnoul
dc.date.accessioned2025-07-21T06:12:44Z
dc.date.issued2025-03-05
dc.identifier.doi10.1109/ieecon64081.2025.10987880
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/14308
dc.subjectApplication-specific integrated circuit
dc.subjectFPGA prototype
dc.subjectProgrammable Array Logic
dc.subjectProgrammable logic array
dc.subject.classificationEmbedded Systems Design Techniques
dc.titleEvaluation of Multi-Bit Input Logic Blocks in RTL-Designed FPGA Architecture: A Framework for FPGA and ASIC Integration
dc.typeArticle

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