Design of a low-power wide dynamic range CMOS RF power detector

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dc.contributor.authorThanachayanont, A.
dc.date.accessioned2026-08-06T10:12:15Z
dc.date.available2026-08-06T10:12:15Z
dc.date.issued2015-10-02
dc.description.abstractThis article describes the design and implementation of a low-power wide dynamic range radio-frequency power detector in a standard 0.18-µm complementary metal-oxide-semiconductor process. The proposed circuit includes a root-mean-square (RMS) power detector and a logarithmic amplifier. The RMS power detector exploits the non-linear characteristic of metal-oxide-semiconductor field-effect transistor to realise the RMS conversion. Since the output of the RMS power detector is a DC voltage, the following logarithmic amplifier does not require wide operating bandwidth, thus allowing simple circuit realisation with minimum power dissipation. Simple differential amplifier is used to realise the limiting gain stage. Post-layout simulation results showed that the proposed circuit was able to detect input power from −70 dBm to −20 dBm, with signal frequencies ranging from 0.5 GHz to 3.0 GHz, while dissipating 0.9 mW under a 1.8-V power supply voltage.
dc.identifier.citationInternational Journal of Electronics Letters, 3(4), 213-224, 2015
dc.identifier.doi10.1080/00207217.2014.917717
dc.identifier.issn21681724
dc.identifier.other2-s2.0-84940691942
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/6434
dc.sourceInternational Journal of Electronics Letters
dc.subjectlimiting amplifier
dc.subjectlogarithmic amplifier
dc.subjectlow power
dc.subjectRF power detector
dc.subjectRMS power detector
dc.titleDesign of a low-power wide dynamic range CMOS RF power detector
dc.typeArticle

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