Analog median filtering circuit using CMOS three-input max/min cell

This paper presents a current-mode design technique for complementary metal oxide semiconductor (CMOS) implementation of an analog median filtering circuit for real-time signal processing. The proposed three-input median filtering circuit consists of three-input maximum/ minimum (max/min) cell, dual-output current mirrors, and current summation. The max/min cell used is based on an existing multiple-input max/min circuit for simultaneously determining the maximum and minimum values of input signals to overcome the limitations of tree realization by using two-input max/min selectors. Additionally, transistors used in the max/min cell are biased at the edge of conduction to minimize corner errors. PSPICE simulation results are given to verify the operation of the proposed median filtering circuit.