Analog median filtering circuit using CMOS three-input max/min cell

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dc.contributor.authorWongjan, Anan
dc.contributor.authorJulsereewong, Amphawan
dc.contributor.authorJunsing, Tipparat
dc.date.accessioned2026-08-06T10:20:05Z
dc.date.available2026-08-06T10:20:05Z
dc.date.issued2018-06-08
dc.description.abstractThis paper presents a current-mode design technique for complementary metal oxide semiconductor (CMOS) implementation of an analog median filtering circuit for real-time signal processing. The proposed three-input median filtering circuit consists of three-input maximum/ minimum (max/min) cell, dual-output current mirrors, and current summation. The max/min cell used is based on an existing multiple-input max/min circuit for simultaneously determining the maximum and minimum values of input signals to overcome the limitations of tree realization by using two-input max/min selectors. Additionally, transistors used in the max/min cell are biased at the edge of conduction to minimize corner errors. PSPICE simulation results are given to verify the operation of the proposed median filtering circuit.
dc.identifier.citation2018 3rd International Conference on Control and Robotics Engineering Iccre 2018, 155-159, 2018
dc.identifier.doi10.1109/ICCRE.2018.8376454
dc.identifier.other2-s2.0-85050030533
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/8611
dc.source2018 3rd International Conference on Control and Robotics Engineering Iccre 2018
dc.subjectanalog signal processing
dc.subjectCMOS current-mode circuit
dc.subjectmax/min cell
dc.subjectmedian filtering circuit
dc.subjectsummation
dc.titleAnalog median filtering circuit using CMOS three-input max/min cell
dc.typeConference Paper

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