Extraction Methodology and Junction Capacitance Model of PMOSFET in VLSI

Simple item page
dc.contributor.authorItsariya Nissai
dc.contributor.authorAnucha Ruangphanit
dc.contributor.authorNaratip Vittayakorn
dc.contributor.authorRangson Muanghlua
dc.date.accessioned2025-07-21T06:03:11Z
dc.date.issued2020-03-01
dc.identifier.doi10.1109/ieecon48109.2020.229456
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/9248
dc.subjectPerimeter
dc.subjectDiffusion capacitance
dc.subjectLOCOS
dc.subject.classificationThin-Film Transistor Technologies
dc.titleExtraction Methodology and Junction Capacitance Model of PMOSFET in VLSI
dc.typeArticle

Files

Collections

All