1.2 v Differential Difference Current Conveyor Using MIGD MOST Technique

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dc.contributor.authorPhatsornsiri, Punnavich
dc.contributor.authorTorteanchai, Usa
dc.contributor.authorRattanasuttikan, Manurak
dc.contributor.authorJongchanachavawat, Wirote
dc.contributor.authorKumngern, Montree
dc.contributor.authorKhateb, Fabian
dc.date.accessioned2026-08-06T10:35:25Z
dc.date.available2026-08-06T10:35:25Z
dc.date.issued2022-01-01
dc.description.abstractThis paper presents a new differential difference current conveyor (DDCC) using multiple-input gate-driven MOS transistor (MIGD MOST) technique. The MIGD MOST technique can be reduced the number of transistor differential pair. The differential input stage is implemented by flipped voltage follower to obtain low power supply requirements. Thus, the proposed DDCC is capable to working with a supply voltage of 1.2 V and it consumes a 44.2 μW of power dissipation. The simulations were performed with PSPICE using the 0.18 μm CMOS technology to prove the workability of the new circuit.
dc.identifier.citation19th International Conference on Electrical Engineering Electronics Computer Telecommunications and Information Technology Ecti Con 2022, 2022
dc.identifier.doi10.1109/ECTI-CON54298.2022.9795466
dc.identifier.other2-s2.0-85133398121
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/12794
dc.source19th International Conference on Electrical Engineering Electronics Computer Telecommunications and Information Technology Ecti Con 2022
dc.subjectdifferential difference current conveyor
dc.subjectlow-voltage low-power
dc.subjectmultiple-input MOS transistor
dc.title1.2 v Differential Difference Current Conveyor Using MIGD MOST Technique
dc.typeConference Paper

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