A logic block for wave-pipelining

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dc.contributor.authorSato, Tomoaki
dc.contributor.authorChivapreecha, Sorawat
dc.contributor.authorMoungnoul, Phichet
dc.date.accessioned2026-08-06T10:07:51Z
dc.date.available2026-08-06T10:07:51Z
dc.date.issued2013-12-01
dc.description.abstractAn FPGA (Field-Programmable Gate Array) device is selected in order to shorten the development life cycle of a processor. Using the FPGA is disadvantageous than using custom LSI (Large-Scale Integrated circuit) in terms of power consumption and operating frequency. That is, circuit design in the FPGA is required to design methods for high-speed and low-power operations. Wave-pipeline is one of a circuit design technique for high-speed processing and low power consumption. However, the design method has the problem of consuming a large number of logic blocks. To solve this problem, a logic block for wave-pipelining is proposed. The logic block is developed using 0.18-micron C-MOS (Complementary Metal-Oxide-Semiconductor) technology. A wave-pipelined adder which is made with the logic blocks is evaluated in the chip area. As a result, it is shown that the area of the adder which use the logic blocks is less than that of the adder without the logic blocks.
dc.identifier.citationImeti 2013 6th International Multi Conference on Engineering and Technological Innovation Proceedings, 130-134, 2013
dc.identifier.other2-s2.0-84893130532
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/5213
dc.sourceImeti 2013 6th International Multi Conference on Engineering and Technological Innovation Proceedings
dc.subjectBuffer
dc.subjectFPGA
dc.subjectLogic bloc
dc.subjectSystem lsi
dc.subjectTiming
dc.subjectWave-Pipeline
dc.titleA logic block for wave-pipelining
dc.typeConference Paper

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