An FPGA Architecture for ASIC-FPGA Co-design to Streamline Processing of IDSs

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dc.contributor.authorTomoaki Sato
dc.contributor.authorSorawat Chivapreecha
dc.contributor.authorPhichet Moungnoul
dc.contributor.authorKohji Higuchi
dc.date.accessioned2025-07-21T05:57:17Z
dc.date.issued2016-10-01
dc.identifier.doi10.1109/cts.2016.0079
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/5951
dc.subjectApplication-specific integrated circuit
dc.subjectFPGA prototype
dc.subjectGate array
dc.subject.classificationNetwork Packet Processing and Optimization
dc.titleAn FPGA Architecture for ASIC-FPGA Co-design to Streamline Processing of IDSs
dc.typeArticle

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