OTA-based high frequency CMOS multiplier and squaring circuit

Abstract

A gigahertz analog multiplier based on OTA and squaring is proposed. The multiplier has gigahertz frequency response is suitable to use in communication system. The circuit is based on 0.18 mum CMOS technology simulated using PSPICE level 7. This technique provides; wide dynamic range, GHz-bandwidth response and low power consumption. The proposed circuit has been simulated with PSPICE and achieved -3 dB bandwidth of 3.96 GHz. The total power dissipation is 0.588 mW with plusmn1 V power supply voltages..