KMITL
Permanent URI for this communityhttps://dspace.kmitl.ac.th/handle/kmitl/1
Browse
3 results
Search Results
- Some of the metrics are blocked by yourconsent settings
Item type:Publication, Negative differential conductance & hot-carrier avalanching in monolayer WS2 FETs(2017-12-01) ;He, G. ;Nathawat, J. ;Kwan, C. P.; The high field phenomena of inter-valley transfer and avalanching breakdown have long been exploited in devices based on conventional semiconductors. In this Article, we demonstrate the manifestation of these effects in atomically-thin WS<inf>2</inf> field-effect transistors. The negative differential conductance exhibits all of the features familiar from discussions of this phenomenon in bulk semiconductors, including hysteresis in the transistor characteristics and increased noise that is indicative of travelling high-field domains. It is also found to be sensitive to thermal annealing, a result that we attribute to the influence of strain on the energy separation of the different valleys involved in hot-electron transfer. This idea is supported by the results of ensemble Monte Carlo simulations, which highlight the sensitivity of the negative differential conductance to the equilibrium populations of the different valleys. At high drain currents (>10 μA/μm) avalanching breakdown is also observed, and is attributed to trap-assisted inverse Auger scattering. This mechanism is not normally relevant in conventional semiconductors, but is possible in WS<inf>2</inf> due to the narrow width of its energy bands. The various results presented here suggest that WS<inf>2</inf> exhibits strong potential for use in hot-electron devices, including compact high-frequency sources and photonic detectors. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Thermally Assisted Nonvolatile Memory in Monolayer MoS2 Transistors(2016-10-12) ;He, G.; ;Kwan, C. P. ;Lee, Y. H.Nathawat, J.We demonstrate a novel form of thermally-assisted hysteresis in the transfer curves of monolayer MoS<inf>2</inf> FETs, characterized by the appearance of a large gate-voltage window and distinct current levels that differ by a factor of ∼10<sup>2</sup>. The hysteresis emerges for temperatures in excess of 400 K and, from studies in which the gate-voltage sweep parameters are varied, appears to be related to charge injection into the SiO<inf>2</inf> gate dielectric. The thermally-assisted memory is strongly suppressed in equivalent measurements performed on bilayer transistors, suggesting that weak screening in the monolayer system plays a vital role in generating its strongly sensitive response to the charge-injection process. By exploiting the full features of the hysteretic transfer curves, programmable memory operation is demonstrated. The essential principles demonstrated here point the way to a new class of thermally assisted memories based on atomically thin two-dimensional semiconductors. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Conduction Mechanisms in CVD-Grown Monolayer MoS2 Transistors: From Variable-Range Hopping to Velocity Saturation(2015-08-12) ;He, G. ;Ghosh, K. ;Singisetti, U.; We fabricate transistors from chemical vapor deposition-grown monolayer MoS<inf>2</inf> crystals and demonstrate excellent current saturation at large drain voltages (V<inf>d</inf>). The low-field characteristics of these devices indicate that the electron mobility is likely limited by scattering from charged impurities. The current-voltage characteristics exhibit variable range hopping at low V<inf>d</inf> and evidence of velocity saturation at higher V<inf>d</inf>. This work confirms the excellent potential of MoS<inf>2</inf> as a possible channel-replacement material and highlights the role of multiple transport phenomena in governing its transistor action.
