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Author: search.filters.author.Poyai, A.Subject: search.filters.subject.NMOS

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    Development a novel model of threshold voltage of NMOS with temperature dependence and narrow channel width
    (2016-09-06)
    Ruangphanit, A.
    ;
    Poyai, A.
    ;
    Muanghlua, R.
    ;
    Niemcharoen, S.
    ;
    Titiroongruang, W.
    In paper, a development a novel model of threshold voltage of NMOS with temperature dependence and narrow channel width was presented. The models have been developed including the temperature affect of surface potentials, intrinsic carrier concentration and energy band gap. The threshold voltages were measured by the linear extrapolation methodology. The temperature dependence and the body-bias dependence of threshold voltage model of a big NMOS and a narrow channel width NMOS are proposed. The results show that, the measured threshold voltage compared with the development threshold voltage model was low level error.
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    The effects of temperature and device demension of MOSFETs on the DC characteristics of CMOS inverter
    (2012-10-02)
    Ruangphanit, A.
    ;
    Kiddee, K.
    ;
    Poyai, A.
    ;
    Wongprasert, Y.
    ;
    Niemcharoen, S.
    The CMOS fabrication technology requires both n-channel (NMOS) and p-channel (PMOS) transistors be built on the same substrate. To ensure the reliability of the circuit performance over the temperature range, the circuits must be designed accommodate the basic variations parameters as a function of parameter. The temperature dependence of the MOSFET parameters as well as the small dimension effects on the dc characteristics of submicrometer CMOS inverters operated over the temperature range of 27- 125 degree Celsius are presented. The results show that the threshold voltage temperature coefficient (TCV) of both devices increased as the channel width decreased. PMOS has a larger affect more than NMOS because of a buried channel device. The Voltage Transfer Characteristics (VTC) of an inverter shows a symmetrical gate at WR is 2.0. However, the narrow channel effect, threshold voltage matching and ratio B <inf>R</inf> are key problem of CMOS inverter worked. Finally, these results will support the process engineer, circuit designer to improve device performance in the next fabrication. © 2012 IEEE.
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    Substrate bias effects on Drain Induced Barrier Lowering (DIBL) in short channel NMOS FETs
    (2009-07-01)
    Ruangphanit, A.
    ;
    Phongphanchantra, N.
    ;
    Poyai, A.
    ;
    Hruanan, C.
    ;
    Muanghlua, R.
    The substrate biasing characteristics of the Drain-Induced Barrier Lowering (DIBL) effects in short-channel NMOS devices with n+ polysilicon gate that fabricated at TMEC by 0.8 CMOS technology were presented. It was found that by increasing the substrate bias form -1 to -5V, DIBL in NMOS devices with mask channel length (L) from 0.6 to 3.0 micron shows the interesting feature. As the channel length decreased, the threshold voltage shift caused by DIBL first increased with increasing substrate bias and then decreased as the channel length decreased further for the range of L# 0.6 micron. But the DIBL increased with increasing substrate bias for the length of L between 0.8 and 1.2 micron. And almost neglected the substrate bias effect for the range of L > 1.2 micron. The substrate bias effect on subthreshold DIBL coefficient (ETAb) is approximately 3.5, 7.0, 8.0 and 0.7 mV/V for L of 0.8, 1.0, 1.2 and 3.0 micron respectively. Whereas the subthreshold DIBL coefficient (ETA0)is around 44, 10, 5 and 1.25 mV/V respectively. This change in DIBL with substrate bias for a short channel device can be explained as the transition of the surface DIBL effect to the subsurface DIBL effect and the onset of the punchthrough effect. Design considerations of the channel doping profile in short channel NMOS device for substrate bias based on improving the punchthrough and DIBL are also briefly discussed. © 2009, INSInet Publication.