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Author: search.filters.author.Thanachayanont, ApinuntSubject: search.filters.subject.logarithmic ADC

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    A Logarithmic Level-Crossing ADC with Fixed Comparison Window
    (2022-01-01)
    Sirimasakul, Silar
    ;
    Thanachayanont, Apinunt
    This paper describes the design and realization of a logarithmic level-crossing analog-to-digital converter with fixed comparison window. The proposed circuit comprises two comparators, a logarithmic charge-sharing digital-to-analog converter, a control logic circuit, and an up/down counter. The circuit is designed and simulated with process parameters from a 0.18 μm CMOS technology and a 1.8 V power supply voltage. Simulation results showed that the overall circuit exhibited the minimum resolution of 3.9mV and the maximum INL and DNL errors of -0.17LSB and -0.09LSB, respectively.
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    A logarithmic level-crossing ADC
    (2017-11-03)
    Sirimasakul, Silar
    ;
    Thanachayanont, Apinunt
    A 3-bit logarithmic level-crossing analog-to-digital converter (LC-ADC) for biomedical applications is presented. Based on the feedback LC-ADC structure, the proposed circuit is realized by using logarithmic charge-scaling digital-to-analog converters. The circuit is designed and simulated with process parameters from a 0.35-μm CMOS technology and a 1.5-V power supply voltage. Process corner simulation results showed that the INL and DNL errors are within the range of +0.14/-0.09LSB and +0.14/-0.21LSB, respectively.
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    A 6-bit, two-step, successive approximation logarithmic ADC for biomedical applications
    (2016-01-01)
    Sundarasaradula, Yuwadee
    ;
    Constandinou, Timothy G.
    ;
    Thanachayanont, Apinunt
    This paper presents the design and realization of a novel low-power 6-bit successive approximation logarithmic ADC for biomedical applications. A two-step successive approximation method is proposed to obtain a piecewise-linear approximation of the desired logarithmic transfer function. The proposed ADC has been designed and simulated using process parameters from a standard 0.35 μm 2P4M CMOS technology with a single 1.8 V power supply voltage. Simulation results show that, at a sampling rate of 25 kS/s, the proposed ADC consumes 4.36 μW to 14.6 μW (proportional to input amplitudes). The proposed ADC achieves 18.6 pJ/conversion-step, maximum INL of 0.45 LSB, an ENOB of 4.97-bits, and SNDR of 31.7 dB with 1 V full-scale input range.