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Development a novel model of threshold voltage of NMOS with temperature dependence and narrow channel width
(2016-09-06)
Ruangphanit, A.
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Poyai, A.
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Muanghlua, R.
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Niemcharoen, S.
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Titiroongruang, W.
In paper, a development a novel model of threshold voltage of NMOS with temperature dependence and narrow channel width was presented. The models have been developed including the temperature affect of surface potentials, intrinsic carrier concentration and energy band gap. The threshold voltages were measured by the linear extrapolation methodology. The temperature dependence and the body-bias dependence of threshold voltage model of a big NMOS and a narrow channel width NMOS are proposed. The results show that, the measured threshold voltage compared with the development threshold voltage model was low level error.
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Reverse recovery time reworking of fast recovery diodes for industrial production
(2015-06-23)
Itthikusumarn, W.
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Jakphet, W.
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Titiroongruang, W.
For industrial field, cost is one of the most important factors. Especially discrete devices like a fast recovery diodes which are produced by complicated processes. In case of over t<inf>rr</inf> defect, reworking is required to limit the cost which is increased. Owing to simple applied to finished products, electron beam irradiation is presented to rework them. This study have exposed the irradiation to finished fast diodes which high t<inf>rr</inf> (300-400 ns) and considered effects of irradiation on fast diodes after exposed. The result of experiment shows irradiation can reduce t<inf>rr</inf> after exposed depend on irradiation doses from average t<inf>rr</inf> 350ns to 100, 60, 50, 40 and 35ns, for irradiation dose 50, 100, 150, 200, 250 and 300kGy respectively. Notwithstanding fast diodes after exposed were degraded by irradiation. Forward voltage is added double at 50kGy and more in larger doses and reversed leakage current is also slightly increased but did not affect to breakdown voltage.
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The outdoor performance of different PV systems in tropical climate conditions in Thailand
(2015-01-01)
Kittisontirak, S.
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Chumpolrat, K.
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Songtrai, S.
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Udomdachanut, N.
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Hongsingthong, A.
The environmental factors of solar irradiance and module temperature greatly affect the performance of any Photovoltaic (PV) technology. Different PV technologies may react differently to variations in these environmental factors. In this paper, six different PV technologies were measured in the tropical climate of Phra Nakhon Si Ayutthaya, Thailand. The types of PV technologies included in this study are; hydrogenated amorphous silicon single-junction, micromorph, copper indium gallium selenide, monocrystalline silicon, polycrystalline silicon and hetero-junction with intrinsic thin film. The annual average daily solar radiation (Ei) and ambient temperature (Tamb) are approximately 4.9 kWh/m2 and 33.4°C, respectively. The highest output among all the PV systems with the highest monthly Performance Ratio (PR) was obtained with an a-Si:H PV system. The PR was 82.2%. Thin-film technologies maintain a more stable outdoor efficiency compared to crystalline silicon technologies.
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Nanoporous silicon metal-semiconductor-metal photodetector
(2010-01-01)
Atiwongsangthong, N.
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Niemcharoen, S.
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Titiroongruang, W.
In this paper we present a study on the application of nanoporous silicon to an optoelectronic device called a nanoporous silicon metal-semiconductor- metal (MSM) visible light photodetector. This device was fabricated on a nanoporous silicon layer which was formed by electrochemical etching of a silicon wafer in a hydrofluoric acid solution under various anodization conditions such as the resistivity of the silicon wafer, current density, concentration of the hydrofluoric acid solution and anodization time. The structure of this device has two square Al/nanoporous silicon Schottky-barrier junctions on the silicon substrate and the electrode spacing is 500 μm. The experiment will study photoresponse and the response time of a nanoporous silicon MSM photodetector which was fabricated on the various porosity of a nanoporous silicon layer. It is found that when devices are fabricated on a higher porosity nanoporous silicon layer, the photoresponse of the device will expand toward the short-wavelength and the bandwidth of the spectrum response will cover visible light. In addition, it is found that the response time of the device in terms of rise time will decrease. © 2010 World Scientific Publishing Company.
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Multiplication of photocurrent in silicon planar metal-semiconductor-metal structures
(2009-10-22)
Khunkhao, S.
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Titiroongruang, W.
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Niemcharoen, S.
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Ruangphanit, A.
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Phongphanchanthra, N.
DC photocurrent gain properties of planar metal-semiconductor-metal (MSM) optical sensor structures on have been investigated experimentally. The test structure has two co-planar Mo/n-Si Schottky-barrier junctions on silicon of resistivity 9-12 Ω-cm and the electrode separation is 20 μm. The current-voltage (I-V) characteristics measurements under illumination in visible range showed a rapid increase in photocurrent at higher biases examined. From the temperature, the dependence of I-V characteristics and noise measurements, such photocurrent increase was ascribes to avalanche multiplication of carriers photogenerated in the Schottky junction reversed-biased. From low-frequency (10-50kHz) signal measurements, it was found that multiplication factor larger than 100 at 10kHz and 30 at 50kHz was achieved. ©2009 IEEE.
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Effect of exposure energy, focus range, and surface reflection on the photolithography process of contact hole patterning
(2008-10-07)
Sonboonton, R.
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Chaowicharat, E.
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Meesapawong, P.
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Ladthidej, J.
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Titiroongruang, W.
The patterning the contact holes by photolithography process, in this case polysilicon contacts, is the process to produce electrical connection between metal layer and polysilicon gates or metal layer and source/drain. The photolithography process can control size and shape of the contact hole patterns on photoresist before permanently patterned by etching process and then metallization. The contact holes were specified to have the size of 0.8 micron after the photolithography process. In order to achieve this, the process parameters to be considered are exposure energy, focus length of the lens system, and the effect of light reflecting from the film topography underneath. Since in the previous processing step, the attempt to reduce the film topography was done by planarization using BPSG. By adjusting the exposure energy and focus, the optimal condition, to produce 0.8 micron contact holes, was found to be energy of 305 mJ/cm and focus of-1.0 μm. © 2008 IEEE.
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White noise in silicon-based planar metal-semiconductor-metal photodiodes
(2008-10-06)
Khunkhao, S.
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Nanthivatana, P.
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Niemcharoen, S.
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Titiroongruang, W.
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Sato, K.
Low-frequency 3-100 kHz shot noise (white noise) emerging from photoinduced current in Mo/n-Si/Mo structures leaving undepleted region has been observed under different bias and optical intensity conditions. The measurements revealed that the current noise observed depends not only on the illumination intensity levels but also on bias voltage. The current noise observed is expressed as S(ω)=2IΓ2 and analyzed, where I and Γ2 is the average current and noise factor, respectively. The measurements reveal that Γ2 has strong bias dependence, lying Γ2- 0.01 to about unity corresponding to simple shot noise. Such experimental results are explained, stating that the reduction of cross correlation between drift and diffusion currents and autocorrelation of drift current component determining the level of noise occurs with decrease in SCR width bias-dependent. To explain the behavior of observed noise more properly, we propose, in addition to the mechanisms above, that the reduction in autocorrelation effect of each current component plays an important role to decrease the relevant noise to such extremely low levels. © 2008 IEEE.
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Optical-beam profiling by field-controlled metal-semiconductor-metal structures
(2005-10-01)
Kitagawa, K.
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Aoki, T.
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Khunkhao, S.
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Wongprasert, Y.
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Titiroongruang, W.
Optical-beam profiling properties of Schottky-barrier metal-semiconductor- metal (MSM) structures have been investigated experimentally. Making use of a planar molybdenum/n-type silicon/molybdenum (Mo/n-Si/Mo) MSM structure with a wide electrode separation, one-dimensional (1-D) profiling of optical-beam intensity distribution from a helium-neon (He-Ne) laser was carried out. It was confirmed that, in addition to the existing photosensing function, the sensitivity (output photocurrent) of such a structure could be controlled by applying a bias via lateral spreading of the surface space-charge-region (SCR) at the side of the reverse-biased Schottky-junction.
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The MIIS structure capacitor fabricated with high permittivity material
(1999-01-01)
Parnklang, J.
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Surathammanun, J.
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Julprapa, A.
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Riewruja, V.
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Titiroongruang, W.
The MIIS (Metal Insulator Intrinsic Semiconductor) structure capacitor consists of the aluminum, ZnO insulator and n-Type silicon doped with gold atoms. The different electrical characteristics of the devices from the standard MOIS (Metal Oxide Intrinsic Semiconductor) structure capacitor which is fabricated from SiO<inf>2</inf> are presented in this paper. The experimental results show that the threshold voltage of the devices (V<inf>TO</inf>) is smaller than the MOIS devices, the zinc oxide capacitor values (C<inf>OX</inf>) are higher but the total capacitor value (C<inf>T</inf>) of the device does not change.
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CMOS current follower circuits
(1999-01-01)
Parnklang, J.
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Nanthanawanitch, W.
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Titiroongruang, W.
We design current follower circuits (CF) using the CMOS transistor to substitute for the bipolar transistor circuit. The experimental result which uses Spice program found that the input and output impedance of the circuit are 5 kω and 76 Mω respectively. Moreover, the bandwidth of the circuit can be used in a wide range from 0 Hz to 4.1 MHz for CF+ and 0 Hz to 3.4 MHz and the harmonic distortion is less than 4.06% for CF+ and 4.27% for CF/sup-/. We also implement the circuit by using a commercial MOS transistor 4007, which consists of a dual complement of the CMOS transistor. The implemented circuits show that the electrical characteristics are the same as the analysis results from the Spice program.

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