Tooprakai, Sirapop

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Tooprakai, Sirapop
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Tooprakai, Siraphop
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sirapop.to@kmitl.ac.th

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    Efficient Processing Time with Carry-lookahead Adder Memristor Rationed Logic
    (2023-01-01)
    Yamtim, Suparlerk
    ;
    Tooprakai, Siraphop
    This paper presents a novel approach to the design of full adder circuits, leveraging the unique properties of memristors and CMOS logic in a hybrid system. This paper explores the design and operation of memristor-based logic gates, including AND, OR, NAND, and NOR gates, realized through CMOS inverters. This paper further proposes a full adder circuit using Hybrid Memristor-CMOS logic and a carry look-Ahead adder (CLA). Our simulations demonstrate that the proposed full adder circuit outperforms traditional RCA-based circuits in terms of speed. This work contributes to the ongoing discourse in digital electronics, offering fresh perspectives and potential solutions to existing challenges, and hope it will inspire further research in the field of memristor-based digital electronics.
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    Multi-input Memristor Rationed Logic Full Adder Circuit for Efficient Processing Time
    (2022-01-01)
    Yamtim, Suparlerk
    ;
    Tooprakai, Siraphop
    This research proposes a multi-input memristor rationed logic (MRL) 1-bit full adder circuit as an alternative to conventional multi-stage MRL full adders. The proposed multi-input 1-bit full adder circuit consisted of 25 memristors without CMOS transistor. Ripple carry adder was utilized to realize multi-input MRL 8-bit full adder circuit by cascading eight blocks of multi-input MRL 1-bit full adder. The advantages of the multi-input MRL 8-bit full adder include straightforwardness, compactness, and improved delay time. Simulations were carried out by using LTspice simulator and results compared with multi-stage full adders. The multi-input MRL 8-bit full adder circuit achieved higher processing-time efficiency and thereby holds great potential as an alternative to multi-stage full adders. The novelty of this research lies in the use of multi-input MRL technique to realize full adder circuits that effectively mitigate voltage degradation and improve delay time.