Now showing 1 - 1 of 1
  • Some of the metrics are blocked by your 
    Item type:Publication,
    Design high speed and low power hybrid full adder circuit
    (2018-12-24)
    Lueangsongchai, Sathaporn
    ;
    This paper presents 1-bit hybrid full adder cells circuit scheme that high speed and low power consumption. This Full adder cells circuit is designed utilization of XOR gate, XNOR gate, pass logic gate and transmission gate. Result of simulation by HSPICE program based on 16 nm CMOS technology with 0.9V power supply voltage and maximum frequency at 8GHz.