Wisetphanichkij, Sompong

Loading...
Thumbnail Image
Preferred name
Wisetphanichkij, Sompong
Main Affiliation
Email
sompong.wi@kmitl.ac.th

Settings

Now showing 1 - 3 of 3
  • Loading...
    Thumbnail Image
    Some of the metrics are blocked by your 
    consent settings
    Item type:Publication,
    Minimal Realization Plus Current Output CC-based Biquad Circuit
    (2024-06-01)
    Wisetphanichkij, Sompong
    ;
    Angkeaw, Krit
    ;
    Sra-Ium, Napat
    This paper presents a minimal design of a biquad circuit using only one plus current output type-II current conveyor (CCII), one differential voltage current conveyor (DVCC) and grounded passive components. The circuit enables the implementation of all 5 basic filter types: low-pass (LP), band-pass (BP), high-pass (HP), band-stop (BS) and all-pass (AP) by selecting and adding input and output currents with no component matching constraints. Moreover, the circuit parameters ω<inf>0</inf> and Q can be set simply by adjusting the circuit components. The proposed biquad circuit performance has very low sensitivity to circuit components due to its simple structure and a small number of devices (2 active and 4 grounded passive components). This allows the circuit to work at high frequencies. Non-ideal and parasitic effects are investigated and discussed. The performance of the proposed topology was evaluated through PSPICE simulator using the 0.18 μm CMOS technology from the Taiwan Semiconductor Manufacturing Company (TSMC).
  • Loading...
    Thumbnail Image
    Some of the metrics are blocked by your 
    consent settings
    Item type:Publication,
    High-speed and low-power ECL circuits design based on BiCMOS technology
    (1998-12-01)
    Wisetphanichkij, Sompong
    ;
    Dejhan, Kobchai
    ;
    Cheevasuvit, Fusak
    This paper proposes the high speed digital circuit design techniques in order to obtain the small circuit area and low power dissipation. The proposed techniques are a developed feedback controlled current source-active pull down-emitter coupled logic (FCCS-APD-ECL) and a current mirror biasing circuit of gated diode-active pull down-emitter coupled logic (GD-APD-ECL). The technique of FCCS-APD-ECL is used to obtain small circuit chip area and low power dissipation, the technique of GD-APD-ECL is used to obtain the high speed of the circuit. Both proposed circuits performances are carried out.
  • Loading...
    Thumbnail Image
    Some of the metrics are blocked by your 
    consent settings
    Item type:Publication,
    The combinational and sequential adiabatic circuit design and its applications
    (2009-04-08)
    Wisetphanichkij, Sompong
    ;
    Dejhan, Kobchai
    In this paper, a new design of adiabatic circuit, called the quasi-static efficient charge recovery logic (QSECRL) is proposed. To achieve minimum energy consumption, this paper proposes a technique to reduce channel resistance and remove diodes from the signal path. This design method can be implemented in both combination logic and sequential logic. The counter circuit and the 8-bit carry look-ahead (CLA) circuit, a more complex circuit, are selected to evaluate this proposed design. All simulations in this paper have been implemented by SPICE with the 0.8 μm MOSIS technology MOS transistor model under 2-volt (peak-peak) sinusoidal power-clock supply. The results show significantly improved performance of the 8-bit CLA circuit with 20-30 fJ and 70 fJ energy consumption at 10-100 MHz and 500 MHz operating frequency, respectively. © Birkhäuser Boston 2009.