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    Generalized Pascal matrices, inverses, computations and properties using one-to-one rational polynomial s-z transformations
    (2008-01-01)
    Deng, Tian Bo
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    Dejhan, Kobchai
    This paper proposes a one-to-one mapping between the coefficients of continuous-time (s-domain) and discrete-time (z-domain) IIR transfer functions such that the s-domain numerator/denominator coefficients can be uniquely mapped to the z-domain numerator/denominator coefficients. The one-to-one mapping provides a firm basis for proving the inverses of the so-called generalized Pascal matrices from various first-order s-z transformations. We also derive recurrence formulas for recursively determining the inner elements of the generalized Pascal matrices from their boundary ones. Consequently, all the elements of the whole generalized Pascal matrix can be easily generated through utilizing their neighbourhood, which can be exploited for further simplifying the Pascal matrix generations. Finally, we reveal and prove some interesting properties of the generalized Pascal matrices. © 2008 IEEE.
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    An FPGA-based implementation of variable fractional delay filter
    (2009-10-19)
    Nithirochananont, Ussanai
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    Dejhan, Kobchai
    A variable fractional delay (VFD) filter is widely used in applications such as symbol timing recovery, arbitrary sampling rate conversion and echo cancellation. This paper presents an implementation of variable fractional delay filter on FPGA. The implementation utilizes an efficient structure so called Taylor structure. The main advantage of this structure is to reduce number of multiplier and adder when compared with Farrow structure or modified Farrow structure. The result of implementation will be reported as throughput and area utilization. ©2009 IEEE.
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    Design of multiplierless elliptic narrowband IIR digital filter based on sensitivity analysis
    (2004-12-01) ; ;
    Khunaworawet, Tanawut
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    Ruangrangsan, Teerasak
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    Dejhan, Kobchai
    In this paper, we present a technique for the design of narrow-band multiplierless IIR filter based on sensitivity analysis. All the multiplication constants in proposed filter structure are implemented with a small number of shift registers and adders. It is shown in the paper that by appropriated design of the elliptic minimal Q - factor (EMQF) prototyped transfer function, (n+1)/2 multiplication constants of highest sensitivity can be implemented without quantization. The quantization of the remaining (n-1)/2 less-sensitivity constants is performed using phase-tolerence scheme.
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    Design and implementation of biquad digital filter
    (2003-01-01)
    Pradabpet, C.
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    Yimman, S.
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    Hinjit, W.
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    Dejhan, K.
    This paper presents a design and implementation of biquad digital filter based on poles-zeros placement on a unit circle of z-plane. The proposed digital filter can be given three frequency-responses as lowpass filter (LPF), highpass filter (HPF) and bandpass filter (BPF) at the same time. In the design process the Matlab program was used, for real world implementation by using TMS320C31 DSP board. The experimental results shown by the dynamic signal analyzer to indicate that the obtained frequency responses give the same results as design specifications.
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    Adaptive equalization architecture using distributed arithmetic for partial response channels
    (2006-12-01) ;
    Jaruvarakul, Aungkana
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    Jaruvarakul, Nivat
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    Dejhan, Kobchai
    This paper proposes a design and implementation of transversal adaptive digital filter using LMS (Least Mean Squares) adaptive algorithm. The filter structure is based on Distributed Arithmetic (DA), which is able to calculate the inner product by shifting, and accumulating of partial products and storing in look-up table, also the desired adaptive digital filter will be multiplierless filter. In addition, the hardware implementation uses VHDL (Very high-speed integrated circuit Hardware Description Language) and synthesis using FLEX10K Altera FPGA (Field Programmable Gate Array) as target technology and uses Leonardo Spectrum and MAX+plusII program for overall development. The results of this design are shown that the speed performance and used area of FPGA. The experimental results are presented to demonstrate the feasibility of the desired adaptive digital filter.. © 2006 IEEE.
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    Bilinear s-z with frequency transformation using pascal matrix operation
    (2005-12-01) ;
    Sriyapong, Songkran
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    Junnapiya, Somyot
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    Dejhan, Kobchai
    This paper presents an alternative method used for analog domain to digital domain transformation based on bilinear transform. The Pascal matrix is used to transform analog transfer function on s plane to digital transfer function on z plane. Moreover, the frequency transformation from normalized analog low-pass filter prototype to digital low-pass, high-pass, band-pass and band-stop filter will be considered incorporate to Pascal matrix operation. This method can be cleared the computation complexity of original bilinear transform, especially to solve the difficulty in case of higher order of digital filter because all of computation use matrix operation. Therefore, it is easy and appropriate to program this method on personal computer or scientific calculator. © 2005 IEEE.
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    PAPR reduction in OFDM systems using SLM cascade with APPR methods
    (2008-10-06)
    Eupree, K.
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    Dejhan, K.
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    Pradabpet, C.
    In this paper, we proposed a new PAPR reduction technique using selective mapping (SLM) cascade with adaptive peak power reduction (APPR) methods. This technique is used in a system based on Orthogonal Frequency Division Multiplexing (OFDM). OFDM has many orthogonally modulated subcarriers which unexpectedly produce a peak to average power ratio (PAPR) and tend to reduce the power efficiency of a RF amplifier. A sequence of input data is rearranged by SLM for the reduction of PAPR and then fed into the APPR process in the proposed system. The APPR method controls the peak levels of the modulation signal by an adaptive algorithm. It reduces modulation signals over a predefined range. In simulation results, the proposed method has shown better PAPR reduction compared to the SLM and the APPR. ©2008 IEEE.
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    Unified Pascal matrix for first-order s-z domain transformations
    (2009-06-16)
    Deng, Tian Bo
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    Dejhan, Kobchai
    The so-called generalized Pascal matrix is used for transforming a continuous-time (CT) linear system (filter) into a discrete-time (DT) one. This paper derives an explicit expression for a new generalized Pascal matrix called unified Pascal matrixfrom a unified first-order s-z transformation model and rigorously proves the inverses for various first-order s-z transformations. After deriving a recurrence formula for recursively generating the inner elements of the unified Pascal matrix from its boundary elements, we also show that the recurrence formula leads to computationally unstable solutions for high-order systems due to the so-called catastrophic cancellation in numerical computation, but the unstable problem can be solved through partitioning the whole unified Pascal matrix into several small matrices (submatrices) and then using the recurrence formula to compute the submatrices individually from their boundary elements. This operation almost retains the same computational complexity while guarantees numerically stable solutions. Moreover, an interesting property of the unified Pascal matrix is proved. © 2009 IEEE.
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    Even order biquad digital filter design using pascal matrix
    (2008-12-01)
    Srisangngam, Pichet
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    Dejhan, Kobchai
    This paper presents new design method and structure of IIR digital filter. The new design method is based on bilinear s-z transformation and Pascal matrix theorem. These theories are used to transform the normalized analog transfer functions to digital transfer functions. The structure of IIR digital filter is modified for even order biquad digital filter which can give frequency response simultaneously as low-pass, high-pass, band-pass and band-stop filtering. The new structure use delay units the same as single frequency response IIR digital filters that has same order.I © 2008 IEEE.
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    A CMOS median filter circuit design
    (2006-12-01)
    Noisuwan, Chartchai
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    Nakasuwan, Jintana
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    Knobnob, Boonying
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    Dejhan, Kobchai
    This paper proposes a median filter circuit design, which the operations are in current mode and based on CMOS technology. Its structure consists of three main parts, the first part is current average circuit, second part is current absolute value circuit, and third part is current minimum circuit. The results of this circuit can be shown using the PSpice simulation program to demonstrate the performances of this circuit. © 2006 IEEE.