Chivapreecha, Sorawat
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Preferred name
Chivapreecha, Sorawat
Alternative Name
Chivapreecha, S.
Chivapreecha, Sorwat
Main Affiliation
Email
sorawat.ch@kmitl.ac.th
3 results
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Item type:Publication, A connection block implemented in the RTL design for delay time equalization of wave-pipelining(2015-01-01); Field-programmable gate arrays (FPGAS) which have many advantages are used in various devices. Use of the FPGAS is not only prototyping and verification of circuits but also an important part of the commercial products. A CPU of hardcore is required in the FPGAS. But it has a problem with the architecture of the CPU is limited. The method of solving these problems is developing a system on a chip (SoC) which is equipped with FPGAS and a customized CPU. From the view point of ease of design and shortening a design period, development techniques on a register-transfer level (RTL) using a standard cell library are essential. On the other hand, applying this method without using a design technique has a problem in terms of throughput. In this paper, a connection block for routing using wave-pipeline technique is proposed to solve the throughput problems. This block is evaluated, and it is shown that it is useful for wave pipeline operation. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, A crossbar switch circuit design for reconfigurable wave-pipelined circuits(2014-01-01); This paper states crossbar switches which are used for the efficient design in reconfigurable wave-pipelined circuits. In the hardware- and host-based IPS (Intrusion Prevention System) which is used in mobile computing, reconfigurable circuits for intrusion detecting are implemented and their design requires techniques for highspeed and low-power operations. Wave-pipeline is a technique for realizing them. On the other hand, using it makes a problem that consumes a large amount of logic block in a conventional FPGA (Field-Programmable Gate Array). To solve this problem, the authors have developed a logic block for wave-pipelining. However, a crossbar switch for controlling the logic blocks to be used has not been developed. In this paper, the crossbar switches are developed in RTL (Register Transfer Level) and delay times, area and power are calculated. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Throughput of a Firewall Unit on FPGAS Developed by the RTL Design Methodology(2017-10-19); ; Higuchi, KohjiThe transmission speed of mobile communication systems for mobile and IoT (Internet of things) devices is getting faster. Advanced, high-speed and low-power processing on network packets are needed in these devices. To realize these performances in the devices, the authors have proposed FPGAS (field-programmable gate arrays) which are developed by the RTL (register-Transfer level) design methodology. As an application of the FPGAS for mobile communication systems, a firewall unit has been developed. However, the function of the firewall unit is only packet filtering. A function for deleting a packet passing through an unauthorized port has not been realized. In this paper, the authors design the firewall unit with the function of deleting the packet. The throughputs of the firewall unit are shown. Thus, it is clarified that high throughput can be accommodated.