Kumngern, Montree

Preferred name

Kumngern, Montree

Alternative Name

KUMNGERN, Montree

Kumngern, M.

Main Affiliation

School of Engineering

montree.ku@kmitl.ac.th

Now showing 1 - 10 of 82

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Mem-Elements Emulator Design with Experimental Validation and Its Application
(2021-01-01)
Raj, Niranjan
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Ranjan, Rajeev Kumar
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Khateb, Fabian
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Kumngern, Montree
An emulator circuit of Memristor, Memcapacitor, and Meminductor commonly termed as mem-elements has been demonstrated in this article. The circuit has been realized using the technique of current mode, which provides better performance over voltage mode counterparts. The current mode analog building blocks, along with a few passive components, have been used in the presented circuit implementation. The fingerprint characteristics have been observed in both simulation and experimental results, validating the theoretical analysis. The robustness of the presented design has been supported by performing different types of analysis like process corner, temperature, and non-volatility behavior. The mem-elements emulator design has been simulated using $0.18~\mu \text{m}$ TSMC process parameter, and ±1.2 V power supply has been used. The commercial ICs AD844 and CA3080 are used for the experimental demonstration of the proposed mem-elements design by making a prototype on a breadboard. A layout area of $4829~\mu \text{m}^{2}$ , $8098~\mu \text{m}^{2}$ , and $8061~\mu \text{m}^{2}$ respectively is required for the Memristor, Memcapacitor, and meminductor circuit. The power consumed by the mem-elements circuit is also provided. A chaotic has been implemented using mem-elements to show the usefulness of the emulator design.
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Flipped Classroom Based on Active Learning in Digital Communications Course for Science in Technical Education on New Normal
(2023-01-01)
Nonthaputha, Thanat
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Kumngern, Montree
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Kaewwang, Sompong
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Phookwantong, Jirapat
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Thepnarin, Nawaphol
Even the coronavirus disease 2019 (COVID-19) situation has been extricated but it is stilled uncontrollable and spreadable and impacts widely both on economic and academic aspect. The proposed of the study is to investigate and develop the flipped classroom based on active learning for digital communications course students in science in technical education program on new normal. It is designed and focused to prepare when the uncontrollable situation will be occurring. Likewise, this can be taught face-To-face on normal situation. The samples are 70 students who registered in this course and the questionnaire was the research instrument through the simple random sampling technique. The results of this study proved that the students had the highest interested in the active learning through the flipped classroom ($x= 4.89$) and it is flexibility that also can be taught face-To-face and online learning.
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0.3-V Voltage-Mode Versatile First-Order Analog Filter Using Multiple-Input DDTAs
(2023-07-01)
Kumngern, Montree
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Khateb, Fabian
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Kulej, Tomasz
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Steffan, Pavel
This paper presents a versatile first-order analog filter using differential difference transconductance amplifiers (DDTAs). The DDTA employs the bulk-driven (BD) multiple-input MOS transistors technique (MI-MOST) operating in the subthreshold region. This results in low-voltage and low-power operational capability. Therefore, the DDTA, designed using 130 nm CMOS technology from UMC in the Cadence environment, operates with 0.3 V and consumes 357.4 nW. Unlike previous works, the proposed versatile first-order analog filter provides first-order transfer functions of low-pass, high-pass, and all-pass filters within a single topology. The non-inverting, inverting, and voltage gain of the transfer functions are available for all filters. Furthermore, the proposed structure provides high-input and low-output impedance, which is required for voltage-mode circuits. The pole frequency and voltage gain of the filters can be electronically controlled. The total harmonic distortion of the low-pass filter was calculated as −39.97 dB with an applied sine wave input signal of 50 mV<inf>pp</inf>@ 50 Hz. The proposed filter has been used to realize a quadrature oscillator to confirm the advantages of the new structure.
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Current-Mode Active Filter Using EX-CCCII
(2024-06-01)
Kumngern, Montree
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Khateb, Fabian
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Kulej, Tomasz
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Tooprakai, Siraphop
This paper presents a novel multiple-input and multiple-output current-mode universal analog filter with electronic tuning capability. The proposed circuit uses a single second-generation current-controlled current conveyor with extra-X terminals (EX-CCCII) and two grounded capacitors. The filter can offer five standard filtering functions, namely low-pass, high-pass, band-pass, band-stop, all-pass responses, in the same circuit without changing the internal configuration of the filter by selecting appropriate input and output signals. To obtain the five standard filtering functions, inverted input signal and input matching conditions are absent. The natural frequency of all filter responses can be electronically controlled. The proposed circuit was simulated by SPICE using 0.18 μm CMOS process from Taiwan Semiconductor Manufacturing Company (TSMC). The results of experiments using the integrated circuit operational amplifier AD844 confirm the functionality of the new filter.
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1 V Electronically Tunable Differential Difference Current Conveyors Using Multiple-Input Operational Transconductance Amplifiers
(2024-03-01)
Kumngern, Montree
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Khateb, Fabian
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Kulej, Tomasz
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Langhammer, Lukas
This paper presents electronically tunable current conveyors using low-voltage, low-power, multiple-input operational transconductance amplifiers (MI-OTAs). The MI-OTA is realized using the multiple-input bulk-driven Metal Oxide Semiconductor transistor (MIBD-MOST) technique to achieve minimum power consumption. The MI-OTA also features high linearity, a wide input range, and a simple Complementary Metal Oxide Semiconductor (CMOS). Thus, high-performance electronically tunable current conveyors are obtained. With the MI-OTA-based current conveyor, both an electronically tunable differential difference current conveyor (EDDCC) and a second-generation electronically tunable current conveyor (ECCII) are available. Unlike the conventional differential difference current conveyor (DDCC) and second-generation current conveyor (CCII), the current gains of the EDDCC and ECCII can be controlled by adjusting the transconductance ratio of the current conveyors. The proposed EDDCC has been used to realize a voltage-to-current converter and current-mode universal filter to show the advantages of the current gain of the EDDCC. The proposed current conveyors and their applications are designed and simulated in the Cadence environment using 0.18 μm TSMC (Taiwan Semiconductor Manufacturing Company) CMOS technology. The proposed circuit uses ±0.5 V of power supply and consumes 90 μW of power. The simulation results are presented and confirm the functionality of the proposed circuit and the filter application. Furthermore, the experimental measurement of the EDDCC implemented in the form of a breadboard connection using a commercially available LM13700 device is presented.
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0.5-V High Linear Fully Differential Multiple-Input Bulk-Driven OTA With Effective Self-Embedded CMFB
(2024-01-01)
Khateb, Fabian
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Kulej, Tomasz
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Kumngern, Montree
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Prommee, Pipat
This paper presents a new fully differential multiple-input operational transconductance amplifier (FD MI-OTA) with an effective self-embedded common-mode feedback circuit (CMFB). The circuit employs several design techniques to extend the linearity to the rail-to-rail level, such as a bulk-driven, multiple-input capacitive voltage divider and source degeneration. The circuit uses self-cascode transistors to increase the gain of the OTA from one side and to create a common-mode feedback circuit, needed to control the common-mode output voltage from the other side. Thus, the CMFB is part of the OTA and as a result, its chip area and power consumption remain unchanged. The performance of the proposed circuit was simulated using TSMC s CMOS 0.18 μ m process in the Cadence Virtuoso System Design Platform to validate the performance of the topology. Intensive simulation results based on Monte Carlo and process, voltage, temperature corners were performed to confirm the OTA's performance and the robustness of the CMFB. The circuit operates with a supply voltage of 0.5 V and consumes 17.5nW of power, making it suitable for applications with extremely low voltage supply and low frequency. As an application, a second-order low-pass filter was designed based on the proposed FD MI-OTA.
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0.5-V 281-nW Versatile Mixed-Mode Filter Using Multiple-Input/Output Differential Difference Transconductance Amplifiers
(2024-01-01)
Khateb, Fabian
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Kumngern, Montree
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Kulej, Tomasz
This paper presents a new low-voltage versatile mixed-mode filter which uses a multiple-input/output differential difference transconductance amplifier (MIMO-DDTA). The multiple-input of the DDTA is realized using a multiple-input bulk-driven MOS transistor (MI-BD-MOST) technique to maintain a single differential pair, thereby achieving simple structure with minimal power consumption. In a single topology, the proposed filter can provide five standard filtering functions (low-pass, high-pass, band-pass, band-stop, and all-pass) in four modes: voltage (VM), current (CM), transadmittance (TAM), and transimpedance (TIM). This provides the full capability of a mixed-mode filter (i.e., twenty filter functions). Moreover, the VM filter offers high-input and low-output impedances and the CM filter offers high-output impedance; therefore, no buffer circuit is needed. The natural frequency of all filtering functions can be electronically controlled by a setting current. The voltage supply is 0.5 V and for a 4 nA setting current, the power consumption of the filter was 281 nW. The filter is suitable for low-frequency biomedical and sensor applications that require extremely low supply voltages and nano-watt power consumption. For the VM low-pass filter, the dynamic range was 58.23 dB @ 1% total harmonic distortion. The proposed filter was designed and simulated in the Cadence Virtuoso System Design Platform using the 0.18 µm TSMC CMOS technology.
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A 500-mV, 124.11-nW first-order universal shadow filter based on multiple-input DDTAs
(2026-07-01)
Kumngern, Montree
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Khateb, Fabian
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Kulej, Tomasz
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Thanyaratsakul, Nattapong
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Arbet, Daniel
This paper proposes a novel first-order multifunction filter capable of simultaneously realizing non-inverting and inverting low-pass, high-pass, and all-pass filter responses using multiple-input differential difference transconductance amplifiers (MI-DDTAs). The design leverages the shadow filter technique, enabling electronic tuning of the pole frequency across all filter responses through an external voltage-controlled amplifier. This approach offers enhanced flexibility and reconfigurability, making it highly attractive for adaptive analog signal processing. The MI-DDTA core is implemented using a multiple-input bulk-driven MOS transistor architecture, optimized for ultra-low-voltage and ultra-low-power operation. Designed in Cadence Virtuoso using the 65 nm TSMC CMOS (1P9M) process, the proposed MI-DDTA occupies a compact silicon area of 171 μm × 119 μm. Operating from a 500 mV supply, the shadow filter achieves a dynamic range of 55.9 dB for a 200 mV<inf>pp</inf> input signal, with total harmonic distortion limited to 1%. Owing to its exceptionally low bias currents, the shadow filter exhibits a total power consumption of only 124.11 nW, making it well suited for energy-constrained biomedical and IoT sensor applications, where low-frequency signal processing, compact implementation, and high energy efficiency are essential. To validate the proposed concept, a discrete prototype was also developed using MI-DDTA configurations built with LM13700 operational transconductance amplifiers. The experimental results confirm the expected filter behavior and demonstrate the feasibility of the proposed design in practical scenarios.
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Development of Online Supervision System for Industrial Education Pre-Teachers
(2021-01-01)
Nonthaputha, Thanat
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Kumngern, Montree
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Prasongjan, Piya
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Torteanchai, Usa
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Thepnarin, Nawaphol
In case of coronavirus disease starting in 2019 situations, it is a novel syndrome virus which caused due to the outbreak of highly dangerous. This virus is easily spreadable to human by human. The one of measures for prevention for the human in coronavirus disease situations that the human has been working from home and decreasing face-to-face contacted. This paper presents the development of online supervision system that instead of traditional supervision or onsite face-to-face supervision for industrial education pre-teacher students. It has been designed on web application to convenient for supervisors, mentors and pre-teacher students. They will send about report, assignment and teaching video on the system. Supervisors and mentors can comment, check the report or assignment and approve pre-teacher video teaching on the web daily or weekly. In addition, the proposed system can be decreased the expenses for official travel and a lot of papers when compare with traditional supervision or onsite face-to-face supervision.
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New Zero Power Memristor Emulator Model and Its Application in Memristive Neural Computation
(2023-01-01)
Kumar, Prashant
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Srivastava, Pushkar
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Ranjan, Rajeev Kumar
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Kumngern, Montree
We present here a simple three P-type MOSFET-based grounded memristor emulator model. The model is designed to achieve zero static power dissipation and is done so by eliminating the external DC supply i.e., no DC bias. The proposed memristor emulator model has extremely low dynamic power dissipation as well which comes to around 175 nW i.e., ∼ 67% improvement compared to recent work. A mathematical analysis is carried out to present the relevance of this design. Simulations were done on Cadence Virtuoso 90 nm technology node and fingerprints of the proposed memristor emulator were obtained. The layout area occupied by the model is approx 1154.69 μ m2 and an external capacitor is connected to add tunability to the circuit. Furthermore, Monte Carlo and corner analysis validate the robust nature of the design. Besides, simulations have been experimentally verified using CD-4007 CMOS integrated circuit (IC) to make the design practically feasible. Furthermore, the design offers advantages such as extremely less overall power consumption and smaller chip area that could possibly pave the path for fabrication using standard CMOS technologies. At last, an application of the proposed model depicting in-memory computation through a memristor emulator crossbar array is presented in brief.

Kumngern, Montree

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