Kasemsuwan, Varakorn

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Kasemsuwan, Varakorn
Alternative Name
Kasemsuwan, V.
Kasemsuwan, Varakom
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Email
varakorn.ka@kmitl.ac.th

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    Low-voltage bulk-driven QFG-regulated self-cascode super MOS transistor
    (2016-09-06)
    Thongleam, Thawatchai
    ;
    Suadet, Apirak
    ;
    Kasemsuwan, Varakorn
    A bulk-driven super MOS transistor (BD-SMT) for low voltage operation is presented. The proposed transistor achieves a high effective transconductance (G<inf>m(eff)</inf>), high effective drain impedance (R<inf>D(eff)</inf>) and low effective source impedance (R<inf>S(eff)</inf>). BD-SMT is designed based on regulated self-cascode and negative feedback techniques. The transistor been designed using a 0.18 μm CMOS technology and operated from a 0.4 V supply with a static power consumption of 12 μW. The simulation results showed higher G<inf>m(eff)</inf>, larger R<inf>D(eff)</inf> and smaller R<inf>S(eff)</inf> as compared to those of simple bulk-driven MOS transistor.
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    A 0.5 volt rail-to-rail CMOS pseudo-differential OTA using simple feed-forward technique
    (2011-08-12)
    Suadet, Apirak
    ;
    Thongleam, Thawatchai
    ;
    Kasemsuwan, Varakorn
    ;
    Vichienchom, Kasin
    This paper presents a low voltage CMOS pseudo differential OTA using simple feed-forward technique. The circuit employs feed-forward technique to suppress the common-mode gain, and positive feedback to enhance the output impedance. The circuit is designed using 0.18 μm CMOS technology under 0.5 V supply. The simulation results show rail-to-rail input/output swing, achieved with low common-mode gain (-35 dB). The output swing of the circuit is 0.3 Vpp. The power dissipation of the circuit is 50 μW. © 2011 IEEE.
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    Low voltage adjustable CMOS Schmitt trigger
    (2011-07-01)
    Singhanath, Pratchayaporn
    ;
    Suadet, Apirak
    ;
    Kanjanop, Arnon
    ;
    Thongleam, Thawatchai
    ;
    Kuankid, Sanya
    This paper presents a low voltage adjustable CMOS Schmitt trigger using dynamic threshold MOS (DTMOS). Cross-coupled inverter with body control is employed to speed up the switching process, and control the intensity of the feedback. The proposed Schmitt trigger has been designed using 0.18 m 0.4 V CMOS technology and analyzed using PSPICE with BSIM3V3 device models. The simulation results show rail-to-rail operation and independently adjustable switching voltages for both low-to-high (V<inf>T(LH)</inf>) and high-to-low (V <inf>T(HL)</inf>) as high as 15 % of the supply voltage. The power dissipation is 0.13 W. © 2011 IEEE.
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    Feedforward bulk-driven class AB fully-differential second-generation current conveyor (FDCCII)
    (2014-01-01)
    Thongleam, Thawatchai
    ;
    Kasemsuwan, Varakorn
    In this paper, a feedforward bulk-driven class AB fully-differential second-generation current conveyer (FDCCII) is presented. Bulk-driven differential pair is employed for the input stage allowing the FDCCII to operate with rail-to-rail operation. Feedfoward technique is also incorporated into input stage to increase the DC gain and minimize the common mode gain. The circuit performance is verified using HSPICE in 0.18 μm CMOS technology. The simulation results show rail-to-rail input and output swings. The DC voltage transfer characteristic between ports Y and X and DC current transfer characteristic between ports X and Z shows good linearity. The bandwidths show 25.7 MHz (V<inf>X</inf>/V<inf>Y</inf>), 30 MHz (I<inf>Z</inf>/I<inf>X</inf>), respectively. The power dissipation is 267.5 μW. © (2014) Trans Tech Publications, Switzerland.
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    A 0.8 V quasi-floating-gate fully differential CMOS op-amp with positive feedback
    (2011-08-12)
    Thongleam, Thawatchai
    ;
    Suadet, Apirak
    ;
    Kasemsuwan, Varakorn
    This paper presents a 0.8 V fully differential CMOS op-amp. The input stage of the circuit is designed using quasi-floating-gate (QFG) transistors with positive feedback, while QFG transistors in the output stage are connected in the class AB configuration. QFG transistors are employed, enabling the circuit to operate under low supply voltage. The proposed amplifier is designed using 0.18 μm CMOS technology, and simulation results show rail-to-rail input and output swings. The open-loop gain is 80.4 dB with the gain-bandwidth product of 8.66 MHz. Phase margin is 45° (C<inf>L</inf>= 20 pF). The CMRR is 107 dB (at 1 kHz) and the power consumption is 54.9 μW. © 2011 IEEE.
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    A 0.8 v class-AB linear OTA using DTMOS for high-frequency applications
    (2011-07-01)
    Suadet, Apirak
    ;
    Thongleam, Thawatchai
    ;
    Kanjanop, Arnon
    ;
    Singhanath, Pratchayaporn
    ;
    Hirunsing, Buncha
    This paper presents a 0.8 V class-AB linear operational transconductance amplifier (OTA) using DTMOS for high-frequency applications. The circuit employs positive feedback to enhance the input impedance, and feed-forward technique to suppress the common-mode gain. The circuit is designed using 0.18 μm CMOS technology under 0.8 V supply. The simulation results show rail-to-rail input/output swing, suppressed common-mode response, and good linearity (less than -48 dB with input 0.6 V<inf>pp</inf>, 5 MHz). The power dissipation is 155 μW. © 2011 IEEE.
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    A 0.5 v class AB quasi FGMOS pseudo fully differential CMOS op-amp with rail-to-rail input/output swing
    (2011-07-01)
    Thongleam, Thawatchai
    ;
    Suadet, Apirak
    ;
    Kanjanop, Arnon
    ;
    Singhanath, Pratchayaporn
    ;
    Hirunsing, Buncha
    This paper presents a 0.5 V pseudo fully differential CMOS op-amp with rail-to-rail input/output swing. The circuit is designed based on class AB input and output stages. In the design, quasi FGMOS transistors are employed. The proposed amplifier is designed using 0.18 μm CMOS technology, and the simulation results show rail-to-rail input and output swings. The open-loop gain and gain-bandwidth product show 73.3 dB and 12.6 MHz. The CMRR is 73.2 dB (at 1 kHz) and the power consumption is 27.9 μW. © 2011 IEEE.
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    An ultra low voltage rail-to-rail DTMOS voltage follower
    (2011-07-01)
    Kanjanop, Arnon
    ;
    Suadet, Apirak
    ;
    Singhanath, Pratchayaporn
    ;
    Thongleam, Thawatchai
    ;
    Kuankid, Sanya
    An ultra low voltage rail-to-rail DTMOS voltage follower is presented. The circuit is developed based on a complementary source follower with a common-source output stage. The circuit is designed using a 0.13 m CMOS technology and SPICE is used to verify the circuit performance. The voltage follower can drive 0.25 V to the 500 with the total harmonic distortion (THD) of 0.4% at the operating frequency of 1 MHz. The bandwidth and power dissipation are 288 MHz and 103 W, respectively. © 2011 IEEE.